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Searched refs:REG_GET (Results 1 – 25 of 41) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c57 REG_GET(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
60 REG_GET(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
63 REG_GET(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
66 REG_GET(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
99 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_dsc_pg_control()
153 REG_GET(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
157 REG_GET(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
161 REG_GET(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
165 REG_GET(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
199 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_hubp_dpp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c57 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dcn301_get_16_bit_backlight_from_pwm()
58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dcn301_get_16_bit_backlight_from_pwm()
60 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm); in dcn301_get_16_bit_backlight_from_pwm()
61 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dcn301_get_16_bit_backlight_from_pwm()
106 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dcn301_panel_cntl_hw_init()
134 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_panel_cntl_hw_init()
163 REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value); in dcn301_is_panel_backlight_on()
173 REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dcn301_is_panel_powered_on()
191 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.c58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dce_get_16_bit_backlight_from_pwm()
59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dce_get_16_bit_backlight_from_pwm()
62 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in dce_get_16_bit_backlight_from_pwm()
63 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dce_get_16_bit_backlight_from_pwm()
99 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_panel_cntl_hw_init()
119 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_panel_cntl_hw_init()
153 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state); in dce_is_panel_backlight_on()
166 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dce_is_panel_powered_on()
184 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_store_backlight_level()
H A Ddce_link_encoder.c286 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); in dce110_get_dig_frontend()
734 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dce110_is_dig_enabled()
1752 REG_GET(DP_MSE_SAT_UPDATE, in dce110_link_encoder_update_mst_stream_allocation_table()
1755 REG_GET(DP_MSE_SAT_UPDATE, in dce110_link_encoder_update_mst_stream_allocation_table()
1775 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dce110_link_encoder_connect_dig_be_to_fe()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c100 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc401_read_state()
101 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc401_read_state()
102 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); in dsc401_read_state()
103 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); in dsc401_read_state()
104 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); in dsc401_read_state()
105 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); in dsc401_read_state()
106 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); in dsc401_read_state()
107 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); in dsc401_read_state()
110 REG_GET(DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, &s->dsc_block_pred_enable); in dsc401_read_state()
111 REG_GET(DSCC_PPS_CONFIG0, LINEBUF_DEPTH, &s->dsc_line_buf_depth); in dsc401_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c147 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc2_read_state()
148 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc2_read_state()
149 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); in dsc2_read_state()
150 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); in dsc2_read_state()
151 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); in dsc2_read_state()
152 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); in dsc2_read_state()
153 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); in dsc2_read_state()
154 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); in dsc2_read_state()
236 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_enable()
259 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_disable()
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.c43 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi4_core_ddc_init()
110 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi4_core_ddc_read()
115 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi4_core_ddc_read()
124 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi4_core_ddc_read()
131 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi4_core_ddc_read()
139 buf[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi4_core_ddc_read()
H A Dhdmi.h280 #define REG_GET(base, idx, start, end) \ macro
287 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
H A Ddsi.c50 #define REG_GET(dsi, idx, start, end) \ macro
146 if (REG_GET(dsi, idx, bitnum, bitnum) == value) in wait_for_bit_change()
153 if (REG_GET(dsi, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1259 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
1730 return REG_GET(dsi, DSI_VC_CTRL(vc), 0, 0); in dsi_vc_is_enabled()
1741 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit) == 0) in dsi_packet_sent_handler_vp()
1763 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit)) { in dsi_sync_vc_vp()
1790 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5) == 0) in dsi_packet_sent_handler_l4()
1809 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5)) { in dsi_sync_vc_l4()
1903 if (REG_GET(dsi, DSI_VC_CTRL(vc), 9, 9) == enable) in dsi_vc_enable_hs()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.c44 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
116 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
121 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
130 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
137 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
145 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
H A Dhdmi.h261 #define REG_GET(base, idx, start, end) \ macro
268 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
H A Ddsi.c111 #define REG_GET(dsidev, idx, start, end) \ macro
502 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
509 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1784 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
2280 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); in dsi_vc_is_enabled()
2291 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) in dsi_packet_sent_handler_vp()
2314 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { in dsi_sync_vc_vp()
2341 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) in dsi_packet_sent_handler_l4()
2360 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { in dsi_sync_vc_l4()
2513 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_long_data()
[all …]
H A Dhdmi5.c317 idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); in read_edid()
701 REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); in hdmi_audio_register()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c177 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); in dwb2_update()
204 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); in dwb2_is_enabled()
205 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); in dwb2_is_enabled()
H A Ddcn20_vmid.c61 REG_GET(PAGE_TABLE_BASE_ADDR_LO32, in dcn20_wait_for_vmid_ready()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/
H A Ddcn20_hubbub.c641 REG_GET(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, &hubbub_state->vm_error_mode); in hubbub2_read_state()
644 REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, &hubbub_state->vm_error_status); in hubbub2_read_state()
645 REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, &hubbub_state->vm_error_vmid); in hubbub2_read_state()
646 REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, &hubbub_state->vm_error_pipe); in hubbub2_read_state()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_vpg.c68 REG_GET(VPG_MEM_PWR, VPG_GSP_MEM_PWR_STATE, &vpg_gsp_mem_pwr_state); in vpg31_poweron()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
H A Ddcn21_hwseq.c59 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_update_page_table_config()
61 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_update_page_table_config()
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_hpd.c76 REG_GET(int_status, in dal_hw_hpd_get_value()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c147 REG_GET(DENTIST_DISPCLK_CNTL, in dcn20_update_clocks_update_dentist()
433 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); in dcn2_read_clocks_from_hw_dentist()
434 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider); in dcn2_read_clocks_from_hw_dentist()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c171 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn302_dsc_pg_control()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
H A Ddcn35_dsc.c96 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc35_enable()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h111 #define REG_GET(reg_name, field, val) \ macro
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c126 REG_GET(OPTC_DATA_SOURCE_SELECT, in optc201_get_optc_source()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c206 REG_GET(CLK4_CLK_PLL_REQ, FbMult_int, &clk_mgr->base.dentist_vco_freq_khz); in dcn201_clk_mgr_construct()

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