Searched refs:Phase (Results 1 – 17 of 17) sorted by relevance
57 Phase 0 = 00058 Phase 1 = 00159 Phase 2 = 01160 Phase 3 = 01061 Phase 4 = 11062 Phase 5 = 11163 Phase 6 = 10164 Phase 7 = 100
29 Phase data has to be collected when temperature and
178 - Phase A: voltage and current (IA + VA)179 - Phase B: voltage and current (IB + VB)180 - Phase C: voltage and current (IC + VC)187 Enable waveform capture for Phase A:228 - Phase A voltage = in_voltage0_raw * in_voltage0_scale = 0.3769 V239 - Phase A active power = in_power0_active_raw * in_power0_scale = 1.386 W
6 # Phase-Locked Loop (PLL) frequency synthesizers27 # Phase-Locked Loop (PLL) frequency synthesizers30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
20 This driver supports TI TPS40422 Dual-Output or Two-Phase Synchronous Buck
25 - Programmable Multi-Phase up to 10 Phases.
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock14 DPLL - Digital Phase Locked Loop is an integrated circuit which in192 Phase offset measurement and adjustment246 Phase adjust (also min and max) values are integers, but measured phase251 Phase offset monitor254 Phase offset measurement is typically performed against the current active255 source. However, some DPLL (Digital Phase-Locked Loop) devices may offer
38 allows for pin controlled PSK Phase Shift Keying
28 3. Clock and PLL (Phase-Locked Loop) configuration
1804 * SCSI Phase2747 * 960MHz Phase-Locked Loop Control 02774 * 960MHz Phase-Locked Loop Control 12815 * 960-MHz Phase-Locked Loop Test Count2825 * 400-MHz Phase-Locked Loop Control 02851 * 400-MHz Phase-Locked Loop Control 12873 * 400-MHz Phase-Locked Loop Test Count
172 04 Phase. Val 00 = 0 deg, Val 40 = 90 degs.
201 enum Phase { enum
180 IEC958 In Phase Inverse
414 2140 Phase 5
649 TerraTec EWX 24/96, EWS 88MT/D, DMX 6Fire, Phase 88;668 7.1 Space/Universe, Phase 22/28; Onkyo SE-90PCI, SE-200PCI;
161 # Phase-align the base time to the start of the next second.
325 * Phase II of GFP_ATOMIC effort. Replaced iocb_mem_pool and