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Searched refs:PNAME (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/clk/samsung/
H A Dclk-exynosautov920.c351 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
352 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
353 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
354 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
355 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
356 PNAME(mout_shared5_pll_p) = { "oscclk", "fout_shared5_pll" };
357 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
359 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
362 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
364 PNAME(mout_clkcmu_acc_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
[all …]
H A Dclk-exynos990.c471 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
472 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
473 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
474 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
475 PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
476 PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
477 PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
478 PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu",
480 PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
482 PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
[all …]
H A Dclk-artpec8.c187 PNAME(mout_clkcmu_bus_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
189 PNAME(mout_clkcmu_bus_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div4",
191 PNAME(mout_clkcmu_core_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
193 PNAME(mout_clkcmu_core_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
195 PNAME(mout_clkcmu_cpucl_switch_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
197 PNAME(mout_clkcmu_fsys_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2",
199 PNAME(mout_clkcmu_fsys_ip_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
201 PNAME(mout_clkcmu_fsys_scan0_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" };
202 PNAME(mout_clkcmu_fsys_scan1_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" };
203 PNAME(mout_clkcmu_imem_imem_p) = { "dout_pll_shared1_div4", "dout_pll_shared0_div3",
[all …]
H A Dclk-exynos4.c283 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
284 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
285 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
286 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
287 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
288 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
289 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
290 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
291 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
292 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
[all …]
H A Dclk-fsd.c185 PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
186 PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
187 PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
188 PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
189 PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
190 PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
191 PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
192 PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" };
193 PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" };
194 PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" };
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-rk3568.c219 PNAME(mux_pll_p) = { "xin24m" };
220 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
221 PNAME(mux_usb480m_phy_p) = { "clk_usbphy0_480m", "clk_usbphy1_480m"};
222 PNAME(mux_armclk_p) = { "apll", "gpll" };
223 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_os…
224 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_os…
225 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_os…
226 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_os…
227 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half …
228 PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_os…
[all …]
H A Dclk-rk3308.c122 PNAME(mux_pll_p) = { "xin24m" };
123 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
124 PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" };
125 PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
126 PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
127 PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" };
128 PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
129 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
130 PNAME(mux_vpll0_vpll1_p) = { "vpll0", "vpll1" };
131 PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
[all …]
H A Dclk-rv1126b.c85 PNAME(mux_pll_p) = { "xin24m" };
86 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
87 PNAME(mux_gpll_aupll_p) = { "gpll", "aupll" };
88 PNAME(mux_gpll_aupll_cpll_p) = { "gpll", "aupll", "cpll" };
89 PNAME(mux_gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
90 PNAME(mux_cpll_24m_p) = { "cpll", "xin24m" };
91 PNAME(mux_24m_gpll_aupll_cpll_p) = { "xin24m", "gpll", "aupll", "cpll" };
92 PNAME(mux_24m_gpll_cpll_p) = { "xin24m", "gpll", "cpll" };
93 PNAME(mux_24m_gpll_aupll_p) = { "xin24m", "gpll", "aupll" };
94 PNAME(mux_sclk_uart_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
[all …]
H A Dclk-px30.c137 PNAME(mux_pll_p) = { "xin24m"};
138 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
139 PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
140 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
141 PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" };
142 PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
143 PNAME(mux_cpll_npll_p) = { "cpll", "npll" };
144 PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
145 PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
146 PNAME(mux_gpll_npll_p) = { "gpll", "npll" };
[all …]
H A Dclk-rk3228.c132 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
134 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
135 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
136 PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
137 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
138 PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
139 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
141 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
142 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
143 PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
[all …]
H A Dclk-rv1108.c119 PNAME(mux_pll_p) = { "xin24m", "xin24m"};
120 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
121 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
122 PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
123 PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
124 PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
125 PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
126 PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
127 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
128 PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
[all …]
H A Dclk-rv1126.c145 PNAME(mux_pll_p) = { "xin24m" };
146 PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
147 PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
148 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
149 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
150 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
151 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
152 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
153 PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
154 PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
[all …]
H A Dclk-rk3588.c425 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
426 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
427 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
428 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
429 PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" };
430 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
431 PNAME(gpll_aupll_p) = { "gpll", "aupll" };
432 PNAME(gpll_lpll_p) = { "gpll", "lpll" };
433 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
434 PNAME(gpll_spll_p) = { "gpll", "spll" };
[all …]
H A Dclk-rk3576.c280 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
281 PNAME(mux_24m_32k_p) = { "xin24m", "xin_osc0_div" };
282 PNAME(mux_armclkl_p) = { "xin24m", "pll_lpll", "lpll" };
283 PNAME(mux_armclkb_p) = { "xin24m", "pll_bpll", "bpll" };
284 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
285 PNAME(cpll_24m_p) = { "cpll", "xin24m" };
286 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
287 PNAME(gpll_spll_p) = { "gpll", "spll" };
288 PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll" };
289 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
[all …]
H A Dclk-rk3328.c143 PNAME(mux_pll_p) = { "xin24m" };
145 PNAME(mux_2plls_p) = { "cpll", "gpll" };
146 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
147 PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
148 PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
149 PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
151 PNAME(mux_4plls_p) = { "cpll", "gpll",
154 PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
156 PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
159 PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" };
[all …]
H A Dclk-rk3506.c108 PNAME(mux_pll_p) = { "xin24m" };
109 PNAME(gpll_v0pll_v1pll_parents_p) = { "gpll", "v0pll", "v1pll" };
110 PNAME(gpll_v0pll_v1pll_g_parents_p) = { "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
111 PNAME(gpll_v0pll_v1pll_div_parents_p) = { "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" };
112 PNAME(xin24m_gpll_v0pll_v1pll_g_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1…
113 PNAME(xin24m_g_gpll_v0pll_v1pll_g_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", …
114 PNAME(xin24m_g_gpll_v0pll_v1pll_div_parents_p) = { "xin24m_gate", "clk_gpll_div", "clk_v0pll_div", …
115 PNAME(xin24m_400k_32k_parents_p) = { "xin24m", "clk_rc", "clk_32k" };
116 PNAME(clk_frac_uart_matrix0_mux_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate"…
117 PNAME(clk_timer0_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai…
[all …]
H A Dclk-rk3036.c115 PNAME(mux_pll_p) = { "xin24m", "xin24m" };
117 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
118 PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
119 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
120 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
121 PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
124 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
126 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
127 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
[all …]
H A Dclk-rk3399.c109 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
111 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
115 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
119 PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
123 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
127 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
129 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
131 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
134 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
135 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
[all …]
H A Dclk-rk3368.c90 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
91 PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" };
92 PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" };
93 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
94 PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"};
95 PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
97 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
98 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
99 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
100 PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
[all …]
H A Dclk-rk3128.c130 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
132 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_div2_ddr" };
133 PNAME(mux_armclk_p) = { "apll_core", "gpll_div2_core" };
134 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
135 PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
137 PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
138 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
139 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
141 PNAME(mux_clk_peri_src_p) = { "gpll", "cpll", "gpll_div2", "gpll_div3" };
142 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
[all …]
H A Dclk-rk3528.c117 PNAME(mux_pll_p) = { "xin24m" };
118 PNAME(mux_armclk) = { "apll", "gpll" };
119 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
120 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
121 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
122 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src",
124 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src",
126 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src",
128 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src",
130 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src",
[all …]
H A Dclk-rk3288.c192 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
193 PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
194 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
195 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
197 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
198 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
199 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
200 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
201 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
203 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
[all …]
/linux/drivers/clk/pistachio/
H A Dclk-pistachio.c105 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
106 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
107 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
108 PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
109 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
110 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
111 PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
112 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
113 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
114 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
[all …]
H A Dclk.h37 #define PNAME(x) static const char *const x[] __initconst macro
/linux/scripts/
H A Dpatch-kernel62 PNAME=patch-kernel
71 usage: $PNAME [-h] [ sourcedir [ patchdir [ stopversion ] [ -acxx ] ] ]
98 echo "$PNAME does not support reverse patching"

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