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Searched refs:DPLL (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
37 - reg : offsets for the register set for controlling the DPLL.
43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
52 - DPLL mode setting - defining any one or more of the following overrides
54 - ti,low-power-stop : DPLL supports low power stop mode, gating output
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
56 - ti,lock : DPLL locks in programmed rate
[all …]
/linux/drivers/dpll/zl3073x/
H A DKconfig4 tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
6 select DPLL
10 This driver supports Microchip Azurite family DPLL/PTP/SyncE
11 devices that support up to 5 independent DPLL channels,
23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
/linux/Documentation/driver-api/
H A Ddpll.rst7 DPLL chapter
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
97 for automatic-only DPLL devices where mode cannot be switched to manual.
106 by the DPLL
108 used by the DPLL
176 pick a highest priority valid signal and use it to control the DPLL
255 source. However, some DPLL (Digital Phase-Locked Loop) devices may offer
258 message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices.
282 - ``DPLL_FFO_PIN_DEVICE`` - pin vs parent DPLL offset (per-parent)
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h15 #define DPLL 3 macro
/linux/arch/arm/mach-omap2/
H A Dsleep24xx.S60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A DKconfig204 tristate "Mellanox 5th generation network adapters (ConnectX series) DPLL support"
206 select DPLL
208 DPLL support in Mellanox Technologies ConnectX NICs.
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi101 /* derived from 600MHz DPLL */
203 /* derived from 600MHz DPLL */
239 /* derived from 600MHz DPLL */
251 /* derived from 600MHz DPLL */
266 /* derived from 600MHz DPLL */
/linux/Documentation/networking/devlink/
H A Ddevlink-params.rst155 - Clock ID used by the device for registering DPLL devices and pins.
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dice.rst937 There are adapters with DPLL, where pins are connected to the DPLL instead of
940 To see input signal on those PTP pins, you need to configure DPLL properly.
941 Output signal is only visible on DPLL and to send it to the board SMA/U.FL pins,
942 DPLL output pins have to be manually configured.
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h256 #define DPLL 0x034A macro
/linux/drivers/ptp/
H A DKconfig221 select DPLL
/linux/drivers/net/ethernet/intel/
H A DKconfig306 select DPLL
/linux/
H A DMAINTAINERS7912 DPLL SUBSYSTEM