Lines Matching refs:DPLL

7 DPLL  chapter
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
97 for automatic-only DPLL devices where mode cannot be switched to manual.
106   by the DPLL
108   used by the DPLL
176 pick a highest priority valid signal and use it to control the DPLL
255 source. However, some DPLL (Digital Phase-Locked Loop) devices may offer
258 message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices.
282 - ``DPLL_FFO_PIN_DEVICE`` - pin vs parent DPLL offset (per-parent)
292 Some DPLL devices may offer the capability to measure the actual
295 command for supported DPLL devices. In such cases, users can also control
333 from both inputs are used to synchronize the DPLL device. The higher frequency
334 signal is utilized for the loop bandwidth of the DPLL, while the lower frequency
335 signal is used to syntonize the output signal of the DPLL device. This feature