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Searched refs:BANK_SELECT (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/net/ethernet/smsc/
H A Dsmc9194.h60 #define BANK_SELECT 14 macro
204 #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
H A Dsmc91x.h454 #define BANK_SELECT (14 << SMC_IO_SHIFT) macro
897 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
904 SMC_outw(lp, x, ioaddr, BANK_SELECT); \
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v3_0_3_init_cache_regs()
244 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v3_0_3_init_cache_regs()
H A Dgfxhub_v2_0.c234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v2_0_init_cache_regs()
238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v2_0_init_cache_regs()
H A Dgfxhub_v11_5_0.c238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v11_5_0_init_cache_regs()
242 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v11_5_0_init_cache_regs()
H A Dgfxhub_v3_0.c235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v3_0_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v3_0_init_cache_regs()
H A Dgfxhub_v12_0.c243 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v12_0_init_cache_regs()
247 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v12_0_init_cache_regs()
H A Dmmhub_v3_0_2.c252 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v3_0_2_init_cache_regs()
256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v3_0_2_init_cache_regs()
H A Dmmhub_v3_0_1.c252 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v3_0_1_init_cache_regs()
256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v3_0_1_init_cache_regs()
H A Dmmhub_v2_3.c220 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v2_3_init_cache_regs()
224 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v2_3_init_cache_regs()
H A Dmmhub_v4_1_0.c247 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v4_1_0_init_cache_regs()
251 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v4_1_0_init_cache_regs()
H A Dmmhub_v3_0.c253 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v3_0_init_cache_regs()
257 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v3_0_init_cache_regs()
H A Dmmhub_v2_0.c290 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v2_0_init_cache_regs()
294 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v2_0_init_cache_regs()
H A Dmmhub_v1_0.c183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_0_init_cache_regs()
187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_0_init_cache_regs()
H A Dmmhub_v4_2_0.c394 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v4_2_0_mid_init_cache_regs()
398 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v4_2_0_mid_init_cache_regs()
/linux/drivers/net/ethernet/microchip/
H A Dencx24j600_hw.h22 #define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1)) macro
H A Dencx24j600-regmap.c24 int bank_opcode = BANK_SELECT(bank); in encx24j600_switch_bank()
/linux/drivers/gpu/drm/radeon/
H A Drv770.c911 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
957 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
988 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
H A Drv770d.h651 #define BANK_SELECT(x) ((x) << 0) macro
H A Dnid.h121 #define BANK_SELECT(x) ((x) << 0) macro
H A Dcikd.h504 #define BANK_SELECT(x) ((x) << 0) macro
H A Devergreend.h1159 #define BANK_SELECT(x) ((x) << 0) macro
H A Dni.c1276 BANK_SELECT(6) | in cayman_pcie_gart_enable()