| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 214 bool isZExt);
216 MaybeAlign Alignment = std::nullopt, bool isZExt = true,
225 Register ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
934 MaybeAlign Alignment, bool isZExt, in ARMEmitLoad() argument
948 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; in ARMEmitLoad()
950 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; in ARMEmitLoad()
952 if (isZExt) { in ARMEmitLoad()
969 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; in ARMEmitLoad()
971 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; in ARMEmitLoad()
973 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineFrameInfo.h | 179 bool isZExt = false; member
541 return Objects[ObjectIdx+NumFixedObjects].isZExt; in isObjectZExt()
547 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| H A D | TargetCallingConv.h | 74 bool isZExt() const { return IsZExt; } in isZExt() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMachineFunctionInfo.cpp | 72 return LiveIn.second.isZExt(); in isLiveInZExt()
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| H A D | PPCFastISel.cpp | 151 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value, bool isZExt,
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| H A D | PPCISelLowering.cpp | 4501 else if (Flags.isZExt()) in extendArgForPPC64()
7134 else if (Flags.isZExt()) in truncateScalarIntegerArg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 181 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1762 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
1763 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet()
1812 bool isZExt = isa<ZExtInst>(I); in selectIntExt() local
1829 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1915 bool isZExt) { in emitIntExt() argument
1917 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()
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| H A D | MipsISelLowering.cpp | 3065 else if (ArgFlags.isZExt()) in CC_MipsO32()
3077 else if (ArgFlags.isZExt()) in CC_MipsO32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallingConv.td | 16 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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| H A D | AMDGPUCallLowering.cpp | 326 } else if (RetInfo.Flags[0].isZExt()) { in lowerReturnVal()
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| H A D | SIISelLowering.cpp | 2132 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) && VT.bitsLT(MemVT)) { in convertArgType()
2133 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 446 !Flags.isSExt() && !Flags.isZExt()) { in lowerReturn()
735 if (!Flags.isZExt() && !Flags.isSExt()) { in lowerFormalArguments()
1335 if (OrigArg.Ty->isIntegerTy(1) && !Flags.isSExt() && !Flags.isZExt()) { in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 404 } else if (Flags.isZExt()) { in buildCopyFromRegs()
668 if (Flags.isZExt()) in extendOpFromFlags()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanTransforms.cpp | 2869 auto IsExtendedRedValidAndClampRange = [&](unsigned Opcode, bool isZExt, in tryToMatchAndCreateExtendedReduction()
2876 Opcode, isZExt, RedTy, SrcVecTy, Red->getFastMathFlags(), in tryToMatchAndCreateExtendedReduction()
2920 [&](bool isZExt, VPWidenRecipe *Mul, VPWidenCastRecipe *Ext0, in tryToMatchAndCreateMulAccumulateReduction()
2929 Ctx.TTI.getMulAccReductionCost(isZExt, RedTy, SrcVecTy, CostKind); in tryToMatchAndCreateMulAccumulateReduction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCallingConv.td | 12 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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| H A D | SystemZISelLowering.cpp | 11158 !Flags.isSExt() && !Flags.isZExt() && !Flags.isNoExt()) in verifyNarrowIntegerArgs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 228 Register emitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
229 Register emiti1Ext(Register SrcReg, MVT DestVT, bool isZExt);
3918 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
3921 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 388 else if (ArgFlags.isZExt()) in AnalyzeArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 372 else if (ArgFlags.isZExt()) in CC_Lanai32_VarArg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1251 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1262 Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in X86SelectRet()
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| H A D | X86ISelLoweringCall.cpp | 2771 if (Flags.isZExt() != MFI.isObjectZExt(FI) || in MatchingStackOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 365 else if (ArgFlags.isZExt()) in CC_Xtensa_Custom()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 374 if (Flags.isZExt() != MFI.isObjectZExt(FI) || in MatchingStackOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 1448 if (Flags.isZExt()) in getExtOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 6950 (BitWidth < 32 && In.Flags.isZExt())) { in unpackFromRegLoc()
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