189                     bool isZExt);
191                      MaybeAlign Alignment = std::nullopt, bool isZExt = true,
200     unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
899                               MaybeAlign Alignment, bool isZExt,  in ARMEmitLoad()  argument
912           Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;  in ARMEmitLoad()
914           Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;  in ARMEmitLoad()
916         if (isZExt) {  in ARMEmitLoad()
932           Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;  in ARMEmitLoad()
934           Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;  in ARMEmitLoad()
936         Opc = isZExt ? ARM::LDRH : ARM::LDRSH;  in ARMEmitLoad()
1338                              bool isZExt) {  in ARMEmitCmp()  argument
1361       Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();  in ARMEmitCmp()
1423     SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);  in ARMEmitCmp()
1426       SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);  in ARMEmitCmp()
2138       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {  in SelectRet()
2139         SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());  in SelectRet()
2607                                     bool isZExt) {  in ARMEmitIntExt()  argument
2692   bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];  in ARMEmitIntExt()
2694   const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];  in ARMEmitIntExt()
2752   bool isZExt = isa<ZExtInst>(I);  in SelectIntExt()  local
2764   unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);  in SelectIntExt()
2902   uint8_t isZExt     : 1;  member
2932   bool isZExt;  in tryToFoldLoadIntoMI()  local
2938       isZExt = FLE.isZExt;  in tryToFoldLoadIntoMI()
2948   if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlign(), isZExt, false))  in tryToFoldLoadIntoMI()