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Searched refs:createVirtualRegister (Results 1 – 25 of 173) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp194 Register MoveReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass); in selectIntToFP()
221 Register CopyReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass); in selectFPToInt()
224 Register ConvReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass); in selectFPToInt()
253 MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank)); in selectZExt()
258 MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank)); in selectZExt()
325 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
342 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
373 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
401 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
417 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
323 Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select()
367 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
375 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
383 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
395 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
475 Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
478 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
507 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select()
593 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
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H A DMipsISelLowering.cpp1279 Register VReg = MF.getRegInfo().createVirtualRegister(RC); in addLiveIn()
1580 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); in emitAtomicBinary()
1619 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); in emitAtomicBinary()
1620 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); in emitAtomicBinary()
1634 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); in emitAtomicBinary()
1663 Register ScrReg = RegInfo.createVirtualRegister(RC); in emitSignExtendToI32InReg()
1692 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword()
1693 Register ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1694 Register Mask = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1695 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
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H A DMipsMachineFunction.cpp58 MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF)); in getGlobalBaseReg()
84 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
85 Register V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
H A DMips16ISelDAGToDAG.cpp78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
79 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
80 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
H A DMipsSEISelLowering.cpp3061 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3067 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3130 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3136 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3177 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
3184 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
3221 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); in emitCOPY_FD()
3247 Register Wt = RegInfo.createVirtualRegister( in emitINSERT_FW()
3283 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); in emitINSERT_FD()
3369 Register Wt = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
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H A DMipsSEFrameLowering.cpp174 Register VR = MRI.createVirtualRegister(RC); in expandLoadCCond()
189 Register VR = MRI.createVirtualRegister(RC); in expandStoreCCond()
207 Register VR0 = MRI.createVirtualRegister(RC); in expandLoadACC()
208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC()
232 Register VR0 = MRI.createVirtualRegister(RC); in expandStoreACC()
233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC()
265 Register VR0 = MRI.createVirtualRegister(RC); in expandCopyACC()
266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC()
540 Register VR = MF.getRegInfo().createVirtualRegister(RC); in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp447 PS->PoisonReg = MRI->createVirtualRegister(PS->RC); in runOnMachineFunction()
480 PS->InitialReg = MRI->createVirtualRegister(PS->RC); in runOnMachineFunction()
481 Register PredStateSubReg = MRI->createVirtualRegister(&X86::GR32RegClass); in runOnMachineFunction()
754 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC); in tracePredStateThroughCFG()
909 Register Reg = MRI->createVirtualRegister(UnfoldedRC); in unfoldCallAndJumpLoads()
967 TargetAddrSSA.Initialize(MRI->createVirtualRegister(&X86::GR64RegClass)); in tracePredStateThroughIndirectBranches()
1109 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches()
1160 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches()
1182 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC); in tracePredStateThroughIndirectBranches()
1499 Register Reg = MRI->createVirtualRegister(&X86::GR32RegClass); in saveEFLAGS()
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H A DX86FastPreTileConfig.cpp168 Register Zmm = MRI->createVirtualRegister(&X86::VR512RegClass); in InitializeTileConfigStackSpace()
173 Register Ymm = MRI->createVirtualRegister(&X86::VR256RegClass); in InitializeTileConfigStackSpace()
183 Register Xmm = MRI->createVirtualRegister(&X86::VR128RegClass); in InitializeTileConfigStackSpace()
235 TileReg = MRI->createVirtualRegister(&RC); in reload()
240 Register StrideReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in reload()
329 Register StackAddrReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI()
332 Register RowReg = MRI->createVirtualRegister(&X86::GR16RegClass); in convertPHI()
335 Register ColReg = MRI->createVirtualRegister(&X86::GR16RegClass); in convertPHI()
399 MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI()
409 Register StrideReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore()
90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
118 Register R = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTTZ()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp286 SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
296 Register BasePtr = MRI.createVirtualRegister(PtrRC); in emitPrologue()
303 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
311 Register BitmaskReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
355 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
361 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
H A DWebAssemblyPeephole.cpp67 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
100 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DInitUndef.cpp177 Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass); in handleSubReg()
182 Register NewReg = MRI->createVirtualRegister(TargetRegClass); in handleSubReg()
207 Register NewReg = MRI->createVirtualRegister(TargetRegClass); in fixupIllOperand()
229 Register NewDest = MRI->createVirtualRegister(RC); in processBasicBlock()
H A DSwiftErrorValueTracking.cpp37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg()
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt()
133 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in createEntriesInEntryBlock()
242 UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC); in propagateVRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1239 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1252 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1266 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1282 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1296 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1308 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1309 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1326 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect()
1327 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1357 Register Reg = MRI.createVirtualRegister(RI.getBoolRC()); in insertEQ()
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H A DAMDGPUInstructionSelector.cpp158 Register MaskedReg = MRI->createVirtualRegister(SrcRC); in selectCOPY()
249 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64()
347 Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass()); in selectG_ADD_SUB()
370 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB()
371 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB()
383 Register CarryReg = MRI->createVirtualRegister(CarryRC); in selectG_ADD_SUB()
390 .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead) in selectG_ADD_SUB()
701 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectG_BUILD_VECTOR()
888 Register InterpMov = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectInterpP1F16()
1425 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectBallot()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.cpp200 ? MRI.createVirtualRegister(&CSKY::GPRRegClass) in eliminateFrameIndex()
201 : MRI.createVirtualRegister(&CSKY::mGPRRegClass); in eliminateFrameIndex()
221 NewReg = MRI.createVirtualRegister(&CSKY::GPRRegClass); in eliminateFrameIndex()
225 NewReg = MRI.createVirtualRegister(&CSKY::mGPRRegClass); in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp759 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
848 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca()
856 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca()
865 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
873 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
969 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
981 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
1014 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
1026 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
1058 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRBitSpilling()
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H A DPPCVSXCopy.cpp105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.cpp149 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in eliminateFrameIndex()
168 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in eliminateFrameIndex()
181 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp82 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB()
92 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp418 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass); in createDupLane()
433 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
447 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass); in createRegSequence()
465 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createVExt()
477 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass); in createInsertSubreg()
493 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createImplicitDef()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp71 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genElemLoad()
90 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genElemLoad()
124 Register AddrR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp218 ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectShiftMask()
229 ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectShiftMask()
278 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp()
290 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp()
329 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp()
368 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADD_UWOp()
581 Register GPRReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in select()
595 Register GPRRegHigh = MRI.createVirtualRegister(&RISCV::GPRRegClass); in select()
596 Register GPRRegLow = MRI.createVirtualRegister(&RISCV::GPRRegClass); in select()
949 ? MRI.createVirtualRegister(&RISCV::GPRRegClass) in materializeImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp200 ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
279 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
295 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
342 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVSPILL()
360 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVSPILL()
419 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVRELOAD()
437 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVRELOAD()
527 DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex()
676 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); in materializeFrameBaseRegister()

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