158         Register MaskedReg = MRI->createVirtualRegister(SrcRC);  in selectCOPY()
249   Register DstReg = MRI->createVirtualRegister(&SubRC);  in getSubOperand64()
347     Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass());  in selectG_ADD_SUB()
370   Register DstLo = MRI->createVirtualRegister(&HalfRC);  in selectG_ADD_SUB()
371   Register DstHi = MRI->createVirtualRegister(&HalfRC);  in selectG_ADD_SUB()
383     Register CarryReg = MRI->createVirtualRegister(CarryRC);  in selectG_ADD_SUB()
390       .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead)  in selectG_ADD_SUB()
701     Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectG_BUILD_VECTOR()
888   Register InterpMov = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectInterpP1F16()
1425     Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectBallot()
1696     Register M0Base = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectDSGWSIntrinsic()
1977       Register TmpReg = MRI->createVirtualRegister(  in selectImageIntrinsic()
2234     Register LoReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2235     Register HiReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2255       Register TmpReg0 = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2256       Register TmpReg1 = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2257       Register ImmReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2370     Register UndefReg = MRI->createVirtualRegister(SrcRC);  in selectG_SZA_EXT()
2425       Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_SZA_EXT()
2452       Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);  in selectG_SZA_EXT()
2453       Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_SZA_EXT()
2583     Register LoReg = MRI->createVirtualRegister(RC);  in selectG_CONSTANT()
2584     Register HiReg = MRI->createVirtualRegister(RC);  in selectG_CONSTANT()
2638   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2639   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2640   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2641   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2676   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2677   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2678   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2679   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2858       Register TmpReg = MRI->createVirtualRegister(TRI.getBoolRC());  in selectG_BRCOND()
2959   Register HiReg = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2960   Register LoReg = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2975     Register MaskLo = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2976     MaskedLo = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2989     Register MaskHi = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2990     MaskedHi = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
3235     Register IdxReg = MRI->createVirtualRegister(TRI.getVGPR64Class());  in selectBufferLoadLds()
3345       VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalLoadLds()
3487     WaveAddr = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectStackRestore()
3923                  .addDef(MRI.createVirtualRegister(DstRegClass));  in buildRegSequence()
4232     *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectSmrdOffset()
4393                 MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalSAddr()
4459   Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalSAddr()
4512       SAddr = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectScratchSAddr()
4617     Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectMUBUFScratchOffen()
5008   Register RSrc2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in buildRSRC()
5009   Register RSrc3 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in buildRSRC()
5010   Register RSrcHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);  in buildRSRC()
5011   Register RSrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);  in buildRSRC()
5032     RSrcLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);  in buildRSRC()
5117   SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in splitIllegalMUBUFOffset()
5554     TmpReg0 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectNamedBarrierInst()
5569       Register TmpReg1 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectNamedBarrierInst()