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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha256-c64xplus.pl42 ($Xn,$X0,$K)=("B7","B8","B9");
117 || SWAP4 $Xn,$X0
121 || SWAP2 $X0,$X0
138 ADD $X0,$T1,$T1 ; T1 += X[i];
139 || STW $X0,*$Xib++
150 || MV $X0,$X14
151 || SWAP4 $Xn,$X0
152 SWAP2 $X0,$X0
177 ADD $X0,$T1,$T1 ; T1 += X[i];
178 || STW $X0,*$Xib++
[all …]
H A Dsha1-c64xplus.pl40 ($X0,$X2,$X8,$X13) = ("A26","B26","A27","B27");
137 || LDW *${XPA}++,$X0 ; fetches from X ring buffer are
162 || XOR $X0,$X2,$TX0 ; Xupdate XORs are 1 iteration ahead
163 || LDW *${XPA}++,$X0
193 || XOR $X0,$X2,$TX0
194 || LDW *${XPA}++,$X0
230 || XOR $X0,$X2,$TX0
231 || LDW *${XPA}++,$X0
270 || XOR $X0,$X2,$TX0
271 || LDW *${XPA}++,$X0
/freebsd/sys/contrib/libsodium/src/libsodium/crypto_pwhash/scryptsalsa208sha256/sse/
H A Dpwhash_scryptsalsa208sha256_sse.c67 ARX(X1, X0, X3, 7) \
68 ARX(X2, X1, X0, 9) \
70 ARX(X0, X3, X2, 18) \
78 ARX(X3, X0, X1, 7) \
79 ARX(X2, X3, X0, 9) \
81 ARX(X0, X1, X2, 18) \
93 __m128i Y0 = X0 = _mm_xor_si128(X0, (in)[0]); \
100 SALSA20_2ROUNDS(out)[0] = X0 = _mm_add_epi32(X0, Y0); \
114 __m128i X0, X1, X2, X3; in blockmix_salsa8() local
118 X0 = Bin[8 * r - 4]; in blockmix_salsa8()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp135 return Reg >= RISCV::X0 && Reg <= RISCV::X31; in isGPR()
139 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg"); in getRegIndex()
144 if (Reg == RISCV::X0) in setGPRState()
158 if (Reg == RISCV::X0) in getGPRState()
247 return Inst.getOperand(0).getReg() == RISCV::X0; in isTerminator()
260 return Inst.getOperand(0).getReg() != RISCV::X0; in isCall()
272 return Inst.getOperand(0).getReg() == RISCV::X0 && in isReturn()
301 return Inst.getOperand(0).getReg() == RISCV::X0 && in isIndirectBranch()
319 return Inst.getOperand(0).getReg() == RISCV::X0; in isBranchImpl()
321 return Inst.getOperand(0).getReg() == RISCV::X0 && in isBranchImpl()
H A DRISCVMCCodeEmitter.cpp187 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
305 SrcReg2.id() == RISCV::X0) { in expandLongCondBr()
308 SrcReg1.id() == RISCV::X0) { in expandLongCondBr()
336 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol); in expandLongCondBr()
386 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol); in expandQCLongCondBrImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td1029 def : InstAlias<"nop", (ADDI X0, X0, 0), 3>;
1030 def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12:$imm), 2>;
1034 def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
1037 def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>;
1042 def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>;
1043 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
1044 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
1052 (BEQ GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
1054 (BNE GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
1056 (BGE X0, GPR:$rs, bare_simm13_lsb0:$offset)>;
[all …]
H A DRISCVRedundantCopyElimination.cpp76 if (Opc == RISCV::BEQ && Cond[2].isReg() && Cond[2].getReg() == RISCV::X0 && in guaranteesZeroRegInBlock()
79 if (Opc == RISCV::BNE && Cond[2].isReg() && Cond[2].getReg() == RISCV::X0 && in guaranteesZeroRegInBlock()
121 if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) && in optimizeBlock()
H A DRISCVGISel.td61 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty 0))), (SLTU (XLenVT X0), GPR:$rs1)>;
63 (SLTU (XLenVT X0), (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm12)))>;
65 (SLTU (XLenVT X0), (XOR GPR:$rs1, GPR:$rs2))>;
180 def : Pat<(zext (i32 GPR:$src)), (ADD_UW GPR:$src, (XLenVT X0))>;
196 def : Pat<(i32 (zext (i16 GPR:$rs))), (PACK GPR:$rs, (XLenVT X0))>;
198 def : Pat<(i64 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>;
199 def : Pat<(i32 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>;
H A DRISCVInstrPredicates.td15 def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>;
34 CheckRegOperand<2, X0>
146 CheckRegOperand<1, X0>,
H A DRISCVAsmPrinter.cpp300 Hint.addOperand(MCOperand::createReg(RISCV::X0)); in emitNTLHint()
301 Hint.addOperand(MCOperand::createReg(RISCV::X0)); in emitNTLHint()
370 OS << RISCVInstPrinter::getRegisterName(RISCV::X0); in PrintAsmOperand()
532 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addExpr(TargetExpr)); in emitSled()
537 .addReg(RISCV::X0) in emitSled()
538 .addReg(RISCV::X0) in emitSled()
626 std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" + in LowerHWASAN_CHECK_MEMACCESS()
663 if (AddrReg == RISCV::X0) { in LowerKCFI_CHECK()
668 .addReg(RISCV::X0) in LowerKCFI_CHECK()
802 .addReg(RISCV::X0) in EmitHwasanMemaccessSymbols()
[all …]
H A DRISCVInstrInfo.cpp94 .addReg(RISCV::X0) in getNop()
95 .addReg(RISCV::X0) in getNop()
542 OddReg = RISCV::X0; in copyPhysReg()
562 .addReg(RISCV::X0); in copyPhysReg()
899 Register SrcReg = RISCV::X0; in movImm()
921 unsigned SrcRegState = getKillRegState(SrcReg != RISCV::X0) | in movImm()
934 .addReg(RISCV::X0) in movImm()
1446 MI->getOperand(1).getReg() == RISCV::X0) { in isLoadImm()
1460 if (Reg == RISCV::X0) { in isFromLoadImm()
1503 .addReg(RISCV::X0) in optimizeCondBranch()
[all …]
H A DRISCVDeadRegisterDefinitions.cpp93 if (RC && RC->contains(RISCV::X0)) { in runOnMachineFunction()
94 X0Reg = RISCV::X0; in runOnMachineFunction()
H A DRISCVInstrInfoSFB.td35 // We use GPRNoX0 because c.mv cannot encode X0.
198 (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2,
199 (XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>;
202 (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2,
203 (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>;
H A DRISCVInstrInfoC.td707 def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
708 def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;
709 def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
710 def : InstAlias<"c.ntl.all", (C_ADD_HINT X0, X5)>;
906 def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
922 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
955 def : CompressPat<(ADDIW GPRNoX0:$rd, X0, simm6:$imm),
967 def : CompressPat<(JAL X0, bare_simm12_lsb0:$offset),
969 def : CompressPat<(BEQ GPRC:$rs1, X0, bare_simm9_lsb0:$imm),
972 def : CompressPat<(BEQ X0, GPRC:$rs1, bare_simm9_lsb0:$imm),
[all …]
H A DRISCVInstrInfoZfbfmin.td37 // Explicitly select 0 in the condition to X0. The register coalescer doesn't
42 (Select_FPR16_Using_CC_GPR GPR:$lhs, (XLenVT X0),
H A DRISCVInstrInfoZb.td459 def : InstAlias<"zext.w $rd, $rs", (ADD_UW GPR:$rd, GPR:$rs, X0)>;
484 def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>;
488 def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>;
540 (BSET (XLenVT X0), GPR:$rs2)>;
542 (ADDI (XLenVT (BSET (XLenVT X0), GPR:$rs2)), -1)>;
601 (MAX GPR:$rs1, (XLenVT (SUBW (XLenVT X0), GPR:$rs1)))>;
672 def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (PACK GPR:$rs, (XLenVT X0))>;
674 def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (PACKW GPR:$rs, (XLenVT X0))>;
690 (sh2add (XLenVT (ADDI (XLenVT X0), CSImm12MulBy4:$i)),
695 (sh3add (XLenVT (ADDI (XLenVT X0), CSImm12MulBy8:$i)),
[all …]
H A DRISCVFrameLowering.cpp286 .addReg(RISCV::X0) in emitSiFiveCLICPreemptibleSaves()
291 .addReg(RISCV::X0) in emitSiFiveCLICPreemptibleSaves()
296 .addReg(RISCV::X0, RegState::Define) in emitSiFiveCLICPreemptibleSaves()
318 .addReg(RISCV::X0, RegState::Define) in emitSiFiveCLICPreemptibleRestores()
327 .addReg(RISCV::X0, RegState::Define) in emitSiFiveCLICPreemptibleRestores()
332 .addReg(RISCV::X0, RegState::Define) in emitSiFiveCLICPreemptibleRestores()
646 .addReg(RISCV::X0) in allocateAndProbeStackForRVV()
760 .addReg(RISCV::X0) in allocateStack()
779 .addReg(RISCV::X0) in allocateStack()
799 .addReg(RISCV::X0) in allocateStack()
[all …]
H A DRISCVInsertVSETVLI.cpp1061 .addReg(RISCV::X0, RegState::Define | RegState::Dead) in insertVSETVLI()
1062 .addReg(RISCV::X0, RegState::Kill) in insertVSETVLI()
1080 .addReg(RISCV::X0, RegState::Define | RegState::Dead) in insertVSETVLI()
1081 .addReg(RISCV::X0, RegState::Kill) in insertVSETVLI()
1094 .addReg(RISCV::X0, RegState::Define | RegState::Dead) in insertVSETVLI()
1106 .addReg(RISCV::X0, RegState::Kill) in insertVSETVLI()
1118 .addReg(RISCV::X0, RegState::Define | RegState::Dead) in insertVSETVLI()
1635 if (AVL.isReg() && AVL.getReg() != RISCV::X0) { in canMutatePriorConfig()
1781 MI.getOperand(1).setReg(RISCV::X0); in insertReadVL()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td48 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter.
49 // However, on windows, in some circumstances, the SRet is passed in X0 or X1
51 // passed in the alternative register (X0 or X1), not X8:
52 // - X0 for non-instance methods.
63 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>,
100 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
101 [X0, X1, X3, X5]>>>,
106 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
146 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
199 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>,
[all …]
H A DAArch64CleanupLocalDynamicTLSPass.cpp103 TII->get(TargetOpcode::COPY), AArch64::X0) in replaceTLSBaseAddrCall()
130 .addReg(AArch64::X0); in setRegister()
H A DAArch64AsmPrinter.cpp546 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
554 emitMovXReg(AArch64::X0, MI.getOperand(0).getReg()); in LowerPATCHABLE_EVENT_CALL()
565 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
576 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
580 emitMovXReg(AArch64::X0, MI.getOperand(0).getReg()); in LowerPATCHABLE_EVENT_CALL()
586 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
667 AddrIndex = AddrReg - AArch64::X0; in LowerKCFI_CHECK()
713 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" + in LowerHWASAN_CHECK_MEMACCESS()
892 .addReg(AArch64::X0) in emitHwasanMemaccessSymbols()
902 if (Reg != AArch64::X0) in emitHwasanMemaccessSymbols()
[all …]
H A DAArch64CollectLOH.cpp265 static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs"); in mapRegToGPRIndex()
267 if (AArch64::X0 <= Reg && Reg <= AArch64::X28) in mapRegToGPRIndex()
268 return Reg - AArch64::X0; in mapRegToGPRIndex()
/freebsd/sys/contrib/openzfs/module/icp/algs/skein/
H A Dskein_block.c90 uint64_t X0, X1, X2, X3; in Skein_256_Process_Block() local
95 Xptr[0] = &X0; in Skein_256_Process_Block()
124 X0 = w[0] + ks[0]; /* do the first full key injection */ in Skein_256_Process_Block()
146 X0 += ks[((R) + 1) % 5]; /* inject the key schedule value */ \ in Skein_256_Process_Block()
157 X0 += ks[r + (R) + 0]; /* inject the key schedule value */ \ in Skein_256_Process_Block()
236 ctx->X[0] = X0 ^ w[0]; in Skein_256_Process_Block()
294 uint64_t X0, X1, X2, X3, X4, X5, X6, X7; in Skein_512_Process_Block() local
299 Xptr[0] = &X0; in Skein_512_Process_Block()
338 X0 = w[0] + ks[0]; /* do the first full key injection */ in Skein_512_Process_Block()
364 X0 += ks[((R) + 1) % 9]; /* inject the key schedule value */\ in Skein_512_Process_Block()
[all …]
/freebsd/sys/crypto/skein/
H A Dskein_block.c81 u64b_t X0,X1,X2,X3; /* local copy of context vars, for speed */ in Skein_256_Process_Block() local
85 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3; in Skein_256_Process_Block()
107 X0 = w[0] + ks[0]; /* do the first full key injection */ in Skein_256_Process_Block()
128 X0 += ks[((R)+1) % 5]; /* inject the key schedule value */ \ in Skein_256_Process_Block()
139 X0 += ks[r+(R)+0]; /* inject the key schedule value */ \ in Skein_256_Process_Block()
213 ctx->X[0] = X0 ^ w[0]; in Skein_256_Process_Block()
266 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ in Skein_512_Process_Block() local
270 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3; in Skein_512_Process_Block()
299 X0 = w[0] + ks[0]; /* do the first full key injection */ in Skein_512_Process_Block()
324 X0 += ks[((R)+1) % 9]; /* inject the key schedule value */ \ in Skein_512_Process_Block()
[all …]
/freebsd/sys/contrib/libsodium/src/libsodium/crypto_aead/aes256gcm/aesni/
H A Daead_aes256gcm_aesni.c62 __m128i X0, X1, X2, X3; in aesni_key256_expand() local
65 X0 = _mm_loadu_si128((const __m128i *) &key[0]); in aesni_key256_expand()
66 rkeys[i++] = X0; in aesni_key256_expand()
73 X3 = _mm_castps_si128(_mm_shuffle_ps(_mm_castsi128_ps(X3), _mm_castsi128_ps(X0), 0x10)); \ in aesni_key256_expand()
74 X0 = _mm_xor_si128(X0, X3); \ in aesni_key256_expand()
75 X3 = _mm_castps_si128(_mm_shuffle_ps(_mm_castsi128_ps(X3), _mm_castsi128_ps(X0), 0x8c)); \ in aesni_key256_expand()
76 X0 = _mm_xor_si128(_mm_xor_si128(X0, X3), X1); \ in aesni_key256_expand()
77 rkeys[i++] = X0; \ in aesni_key256_expand()
81 X1 = _mm_shuffle_epi32(_mm_aeskeygenassist_si128(X0, (S)), 0xaa); \ in aesni_key256_expand()
332 __m128i X0 = X0_; \

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