| /freebsd/contrib/llvm-project/clang/lib/Headers/ |
| H A D | hvx_hexagon_protos.h | 195 #define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv) argument
206 #define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv) argument
217 #define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv) argument
228 #define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv) argument
283 #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) argument
327 #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) argument
371 #define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv) argument
393 #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) argument
404 #define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv) argument
415 #define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv) argument
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatternsV65.td | 14 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
24 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
34 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
49 RC1:$Vv),
60 RC1:$Vv),
71 RC1:$Vv),
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| H A D | HexagonPatternsHVX.td | 655 def: Pat<(Mfshl HVI8:$Vu, HVI8:$Vv, HVI8:$Vs),
656 (V6_vshuffob (V6_vaslhv (HiVec (V6_vshufoeb $Vu, $Vv)),
658 (V6_vaslhv (LoVec (V6_vshufoeb $Vu, $Vv)),
661 // V60 doesn't produce 0 on shifts by bitwidth, e.g. Vv.h << 16-0
662 def: Pat<(Mfshl HVI16:$Vu, HVI16:$Vv, HVI16:$Vs),
666 (V6_vlsrhv $Vv, (VSubih 16, $Vs))))>;
667 def: Pat<(Mfshl HVI32:$Vu, HVI32:$Vv, HVI32:$Vs),
671 (V6_vlsrwv $Vv, (VSubiw 32, $Vs))))>;
674 // Do it as (Vu << Vs) | (Vv >> (BW-Vs)).
675 // For Vs == 0 becomes Vu | (Vv >> -BW), since the shift amount is
[all …]
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| H A D | HexagonISelDAGToDAGHVX.cpp | 806 // Vdd = vshuffvdd(Vu, Vv, Rt)
807 // Vdd = vdealvdd(Vu, Vv, Rt)
808 // Vd = vpack(Vu, Vv, Size, TakeOdd)
809 // Vd = vshuff(Vu, Vv, Size, TakeOdd)
810 // Vd = vdeal(Vu, Vv, Size, TakeOdd)
811 // Vd = vdealb4w(Vu, Vv)
816 MaskT vshuffvdd(ArrayRef<int> Vu, ArrayRef<int> Vv, unsigned Rt) { in vshuffvdd() argument
819 std::copy(Vv.begin(), Vv.end(), Vdd.begin()); in vshuffvdd()
836 MaskT vdealvdd(ArrayRef<int> Vu, ArrayRef<int> Vv, unsigne argument
856 vpack(ArrayRef<int> Vu,ArrayRef<int> Vv,unsigned Size,bool TakeOdd) vpack() argument
871 vshuff(ArrayRef<int> Vu,ArrayRef<int> Vv,unsigned Size,bool TakeOdd) vshuff() argument
884 vdeal(ArrayRef<int> Vu,ArrayRef<int> Vv,unsigned Size,bool TakeOdd) vdeal() argument
890 vdealb4w(ArrayRef<int> Vu,ArrayRef<int> Vv) vdealb4w() argument
904 MaskT Vu(Length), Vv(Length); mask() local
2702 SDValue Vv = N->getOperand(0); selectVAlign() local
[all...] |
| H A D | HexagonISelLoweringHVX.cpp | 1926 SDValue Vv = Op.getOperand(1); in LowerHvxMulLoHi()
1932 SDValue Lo = DAG.getNode(ISD::MUL, dl, ty(Op), {Vu, Vv}); in LowerHvxMulLoHi()
1942 return emitHvxMulLoHiV62(Vu, SignedVu, Vv, SignedVv, dl, DAG); in LowerHvxMulLoHi()
1948 SDValue Hi = emitHvxMulHsV60(Vu, Vv, dl, DAG); in LowerHvxMulLoHi()
1954 return emitHvxMulLoHiV60(Vu, SignedVu, Vv, SignedVv, dl, DAG); in LowerHvxMulLoHi()
2209 // vlalign(Vu,Vv,Rt) rotates the pair Vu:Vv left by Rt and takes the in LowerHvxMaskedOp()
1927 SDValue Vv = Op.getOperand(1); LowerHvxMulLoHi() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsHexagon.td | 390 // V6_vmpyss_parts(Vu,Vv) = (MulHS(Vu,Vv), Mul(Vu,Vv))
391 // V6_vmpyuu_parts(Vu,Vv) = (MulHU(Vu,Vv), Mul(Vu,Vv))
392 // V6_vmpyus_parts(Vu,Vv) = (MulHUS(Vu,Vv), Mul(Vu,Vv))
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedExynosM5.td | 788 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
794 def : InstRW<[M5WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
833 def : InstRW<[M5WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
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| H A D | AArch64SchedExynosM4.td | 740 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
746 def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
791 def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
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| H A D | AArch64SchedExynosM3.td | 624 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>;
654 def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
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| H A D | AArch64SchedA55.td | 431 def : InstRW<[CortexA55WriteAluVq_4], (instregex "[SU](MAX|MIN)Vv")>;
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| H A D | AArch64SchedTSV110.td | 660 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(MAX|MIN)(NM)?Vv")>;
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| H A D | AArch64SchedA57.td | 491 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
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| H A D | AArch64SchedAmpere1.td | 910 def : InstRW<[Ampere1Write_10cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv.[if](32|64)")>;
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| H A D | AArch64SchedAmpere1B.td | 890 def : InstRW<[Ampere1BWrite_6cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv.[if](32|64)")>;
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| H A D | AArch64SchedOryon.td | 1562 "^(S|U)(MAX|MIN)Vv")>;
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| H A D | AArch64SchedA510.td | 443 def : InstRW<[CortexA510Write<4, CortexA510UnitVALU>], (instregex "[SU](MAX|MIN)Vv")>;
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| /freebsd/contrib/sendmail/ |
| H A D | PGPKEYS | 4379 /Vv+fl5wdw3YVAgKiQCVAwUQNxJ38gx2JIpOldm1AQEeFgQAmK75xIhzb84Qfh9O
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