xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonPatternsV65.td (revision 04eeddc0aa8e0a417a16eaf9d7d095207f4a8623)
10b57cec5SDimitry Andric//==- HexagonPatternsV65.td -------------------------------*- tablegen -*-===//
20b57cec5SDimitry Andric//
30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric//
70b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric
90b57cec5SDimitry Andricmulticlass vgathermh<RegisterClass RC> {
10*04eeddc0SDimitry Andric  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
11*04eeddc0SDimitry Andric  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
120b57cec5SDimitry Andric  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
13*04eeddc0SDimitry Andric                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
14*04eeddc0SDimitry Andric                                IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
150b57cec5SDimitry Andric                           ".error \"should not emit\" ",
160b57cec5SDimitry Andric                           []>;
170b57cec5SDimitry Andric}
180b57cec5SDimitry Andric
190b57cec5SDimitry Andricmulticlass vgathermw<RegisterClass RC> {
20*04eeddc0SDimitry Andric  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
21*04eeddc0SDimitry Andric  mayStore = 1, addrMode = BaseImmOffset, accessSize = WordAccess in
220b57cec5SDimitry Andric  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
23*04eeddc0SDimitry Andric                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
24*04eeddc0SDimitry Andric                                IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
250b57cec5SDimitry Andric                           ".error \"should not emit\" ",
260b57cec5SDimitry Andric                           []>;
270b57cec5SDimitry Andric}
280b57cec5SDimitry Andric
290b57cec5SDimitry Andricmulticlass vgathermhw<RegisterClass RC> {
30*04eeddc0SDimitry Andric  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
31*04eeddc0SDimitry Andric   mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
320b57cec5SDimitry Andric  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
33*04eeddc0SDimitry Andric                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
34*04eeddc0SDimitry Andric                                IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
350b57cec5SDimitry Andric                           ".error \"should not emit\" ",
360b57cec5SDimitry Andric                           []>;
370b57cec5SDimitry Andric}
380b57cec5SDimitry Andric
390b57cec5SDimitry Andricdefm V6_vgathermh_pseudo  : vgathermh<HvxVR>;
400b57cec5SDimitry Andricdefm V6_vgathermw_pseudo  : vgathermw<HvxVR>;
410b57cec5SDimitry Andricdefm V6_vgathermhw_pseudo  : vgathermhw<HvxWR>;
420b57cec5SDimitry Andric
430b57cec5SDimitry Andricmulticlass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
44*04eeddc0SDimitry Andric  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
45*04eeddc0SDimitry Andric  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
460b57cec5SDimitry Andric  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
47*04eeddc0SDimitry Andric                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
48*04eeddc0SDimitry Andric                                RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
49*04eeddc0SDimitry Andric                                RC1:$Vv),
500b57cec5SDimitry Andric                           ".error \"should not emit\" ",
510b57cec5SDimitry Andric                           []>;
520b57cec5SDimitry Andric}
530b57cec5SDimitry Andric
540b57cec5SDimitry Andricmulticlass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
55*04eeddc0SDimitry Andric  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
56*04eeddc0SDimitry Andric  mayStore = 1, addrMode = BaseImmOffset, accessSize = WordAccess in
570b57cec5SDimitry Andric  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
58*04eeddc0SDimitry Andric                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
59*04eeddc0SDimitry Andric                                RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
60*04eeddc0SDimitry Andric                                RC1:$Vv),
610b57cec5SDimitry Andric                           ".error \"should not emit\" ",
620b57cec5SDimitry Andric                           []>;
630b57cec5SDimitry Andric}
640b57cec5SDimitry Andric
650b57cec5SDimitry Andricmulticlass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
66*04eeddc0SDimitry Andric  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
67*04eeddc0SDimitry Andric  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess  in
680b57cec5SDimitry Andric  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
69*04eeddc0SDimitry Andric                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
70*04eeddc0SDimitry Andric                              RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
71*04eeddc0SDimitry Andric                              RC1:$Vv),
720b57cec5SDimitry Andric                           ".error \"should not emit\" ",
730b57cec5SDimitry Andric                           []>;
740b57cec5SDimitry Andric}
750b57cec5SDimitry Andric
760b57cec5SDimitry Andricdefm V6_vgathermhq_pseudo  : vgathermhq<HvxVR, HvxQR>;
770b57cec5SDimitry Andricdefm V6_vgathermwq_pseudo  : vgathermwq<HvxVR, HvxQR>;
780b57cec5SDimitry Andricdefm V6_vgathermhwq_pseudo  : vgathermhwq<HvxWR, HvxQR>;
79