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Searched refs:TEGRA30_CLK_PLL_A_OUT0 (Results 1 – 11 of 11) sorted by relevance

/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra30-car.h212 #define TEGRA30_CLK_PLL_A_OUT0 185 macro
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra-audio-sgtl5000.txt39 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cardhu.dtsi669 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
676 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-colibri.dtsi1055 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1062 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-apalis-v1.1.dtsi1194 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1201 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-apalis.dtsi1177 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1184 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-asus-nexus7-grouper-common.dtsi1226 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1233 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-asus-transformer-common.dtsi1683 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1690 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-lg-x3.dtsi1716 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1723 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-beaver.dts2130 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
2137 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-pegatron-chagall.dts2764 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
2771 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,