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Searched refs:ShiftOpc (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h27 enum ShiftOpc { enum
44 inline StringRef getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
56 inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
98 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
102 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); } in getSORegShOp()
400 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
412 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
413 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
H A DARMMCCodeEmitter.cpp246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
1287 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1325 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1577 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1622 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1731 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
H A DARMInstPrinter.cpp50 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
434 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
H A DARMInstructionSelector.cpp62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
806 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift() argument
810 MIB.addImm(ShiftOpc); in selectShift()
1071 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); in select()
1073 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
1075 return selectShift(ARM_AM::ShiftOpc::lsl, MIB); in select()
H A DARMFastISel.cpp206 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2764 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2791 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2838 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
H A DARMISelDAGToDAG.cpp88 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
541 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
614 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
638 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
760 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
840 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1507 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
3372 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in tryV6T2BitfieldExtractOp()
H A DARMISelLowering.cpp19757 ARM_AM::ShiftOpc ShOpcVal= in getARMIndexedAddressParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp792 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
830 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
847 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
876 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp450 std::optional<ARM_AM::ShiftOpc> tryParseShiftToken();
458 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
638 ParseStatus parsePKHImm(OperandVector &O, ARM_AM::ShiftOpc, int Low,
891 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
901 ARM_AM::ShiftOpc ShiftTy;
911 ARM_AM::ShiftOpc ShiftTy;
918 ARM_AM::ShiftOpc ShiftTy;
3717 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, MCRegister SrcReg, in CreateShiftedRegister()
3731 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, MCRegister SrcReg, in CreateShiftedImmediate()
3893 ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, in CreateMem()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp1145 auto ShiftOpc = ShrAmtC > ShAmtC ? Shr->getOpcode() : Instruction::Shl; in visitShl() local
1151 Value *NewShift = Builder.CreateBinOp(ShiftOpc, X, ShiftDiffC, "sh.diff"); in visitShl()
H A DInstCombineCompares.cpp7857 unsigned ShiftOpc = ShiftI->getOpcode(); in visitICmpInst() local
7858 if ((ExtOpc == Instruction::ZExt && ShiftOpc == Instruction::LShr) || in visitICmpInst()
7859 (ExtOpc == Instruction::SExt && ShiftOpc == Instruction::AShr)) { in visitICmpInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1233 EVT VT, unsigned ShiftOpc, bool MayTransformRotate,
H A DX86ISelLowering.cpp3546 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand() argument
3549 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3568 if (ShiftOpc == ISD::SHL || ShiftOpc == ISD::SRL) { in preferedOpcodeForCmpEqPiecesOfOperand()
3578 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3581 if (ShiftOpc == ISD::SHL) { in preferedOpcodeForCmpEqPiecesOfOperand()
3586 : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3591 return ShiftOrRotateAmt.uge(7) ? (unsigned)ISD::SRL : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3597 return AndMask->getSignificantBits() > 33 ? (unsigned)ISD::SHL : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3600 return ShiftOrRotateAmt.ult(7) ? (unsigned)ISD::SHL : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3606 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1065 unsigned ShiftOpc = Op.getOpcode(); in combineShiftToAVG() local
1077 switch (ShiftOpc) { in combineShiftToAVG()
9785 unsigned ShiftOpc = IsSigned ? ISD::SRA : ISD::SRL; in expandAVG() local
9801 return DAG.getNode(ShiftOpc, dl, VT, Sum, in expandAVG()
9852 DAG.getNode(ShiftOpc, dl, VT, Xor, DAG.getShiftAmountConstant(1, VT, dl)); in expandAVG()
11036 unsigned ShiftOpc = Signed ? ISD::SRA : ISD::SRL; in forceExpandMultiply() local
11037 SDValue LH = DAG.getNode(ShiftOpc, dl, VT, LHS, Shift); in forceExpandMultiply()
11038 SDValue RH = DAG.getNode(ShiftOpc, dl, VT, RHS, Shift); in forceExpandMultiply()
11043 SDValue UH = DAG.getNode(ShiftOpc, dl, VT, U, Shift); in forceExpandMultiply()
11047 SDValue VH = DAG.getNode(ShiftOpc, dl, VT, V, Shift); in forceExpandMultiply()
H A DDAGCombiner.cpp13592 unsigned ShiftOpc = ShiftOrRotate.getOpcode(); in visitSETCC() local
13602 ShiftOpc == ISD::SHL ? (~*AndCMask).isMask() : AndCMask->isMask(); in visitSETCC()
13607 OpVT, ShiftOpc, ShiftCAmt->isPowerOf2(), *ShiftCAmt, AndCMask); in visitSETCC()
13609 if (CanTransform && NewShiftOpc != ShiftOpc) { in visitSETCC()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h924 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand() argument
927 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1680 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegImmOperand()
1720 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegRegOperand()
2119 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; in DecodeAddrMode2IdxInstruction()
2165 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp3751 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
3761 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LsrImm, DL, VT), in tryBitfieldInsertOpFromOr()