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Searched refs:ST1 (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAsmAlias.td522 // Various unary fpstack operations default to operating on ST1.
524 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
525 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
526 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
527 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
528 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
529 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
530 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
531 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
532 def : InstAlias<"fxch", (XCH_F ST1), 0>;
[all …]
H A DX86InstrControl.td20 // ST1 arguments when returning values on the x87 stack.
H A DX86InstrMMX.td153 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
H A DX86RegisterInfo.td440 def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;
H A DX86InstrCompiler.td468 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
488 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp208 {codeview::RegisterId::ST1, X86::ST1}, in initLLVMToSEHAndCVRegMapping()
217 {codeview::RegisterId::ST1, X86::FP1}, in initLLVMToSEHAndCVRegMapping()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td993 (instregex "^ST1(One(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64)|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))$")>;
995 (instregex "^ST1(One(v8b|v4h|v2s|v1d)_POST|(i8|i16|i32|i64)_POST)$")>;
999 (instregex "^ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1004 (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
1013 (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
H A DAArch64SchedKryoDetails.td1848 (instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))$")>;
1854 …(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))_POST$…
1860 (instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1866 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
1872 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
H A DAArch64InstrInfo.td4124 // We must use ST1 to store vectors in big-endian.
4138 // We must use ST1 to store vectors in big-endian.
4226 // We must use ST1 to store vectors in big-endian.
4253 // We must use ST1 to store vectors in big-endian.
4377 // We must use ST1 to store vectors in big-endian.
4403 // We must use ST1 to store vectors in big-endian.
8384 defm ST1 : SIMDSt1Multiple<"st1">;
8584 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
8585 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
8586 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
[all …]
H A DAArch64SchedA510.td1278 def : InstRW<[CortexA510VSt0], (instregex "^ST1[BHWD]_IMM$",
1285 def : InstRW<[CortexA510VSt0], (instregex "^ST1[BWD]$",
H A DAArch64SchedNeoverseV1.td1800 def : InstRW<[V1Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
1804 "^ST1[BWD]$",
H A DAArch64SchedNeoverseN2.td2194 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
2201 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^ST1[BWD]$",
H A DAArch64SchedNeoverseV2.td2717 def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BHWD]_IMM$",
2724 def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BWD]$",
H A DAArch64InstrFormats.td10602 // ST1 instructions have extra "1d" variants.
/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def125 CV_REGISTER(ST1, 129)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp21567 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) { in visitSTORE() local
21569 ST1->isUnindexed() && ST1->isSimple()) { in visitSTORE()
21570 if (OptLevel != CodeGenOptLevel::None && ST1->getBasePtr() == Ptr && in visitSTORE()
21571 ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() && in visitSTORE()
21572 ST->getAddressSpace() == ST1->getAddressSpace()) { in visitSTORE()
21578 if (OptLevel != CodeGenOptLevel::None && ST1->hasOneUse() && in visitSTORE()
21579 !ST1->getBasePtr().isUndef() && in visitSTORE()
21580 ST->getAddressSpace() == ST1->getAddressSpace()) { in visitSTORE()
21586 ST1->getMemoryVT().isScalableVector()) { in visitSTORE()
21587 if (ST1->getBasePtr() == Ptr && in visitSTORE()
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td725 def ST1 : WInst<"vst1", "v*(.!)", "dQdPlQPl">;
H A Darm_sve.td2066 defm ST1 : MultiVecStore<"st1">;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1554 case 1: RegNo = X86::ST1; break; in ParseRegister()