Lines Matching refs:ST1
4124 // We must use ST1 to store vectors in big-endian.
4138 // We must use ST1 to store vectors in big-endian.
4226 // We must use ST1 to store vectors in big-endian.
4253 // We must use ST1 to store vectors in big-endian.
4377 // We must use ST1 to store vectors in big-endian.
4403 // We must use ST1 to store vectors in big-endian.
8384 defm ST1 : SIMDSt1Multiple<"st1">;
8584 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
8585 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
8586 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
8587 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
8591 ValueType VTy, ValueType STy, Instruction ST1>
8595 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
8608 ValueType VTy, ValueType STy, Instruction ST1>
8612 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
8623 ValueType VTy, ValueType STy, Instruction ST1,
8628 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
8634 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
8649 ValueType VTy, ValueType STy, Instruction ST1,
8654 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
8659 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
8688 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
8884 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
8887 // to use LD1/ST1 only to simplify compiler implementation.
8889 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes