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Searched refs:SSE (Results 1 – 25 of 58) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DRangedConstraintManager.cpp49 if (const auto *SSE = dyn_cast<SymSymExpr>(Sym)) { in assumeSym() local
50 BinaryOperator::Opcode Op = SSE->getOpcode(); in assumeSym()
54 if (Loc::isLocType(SSE->getLHS()->getType()) && in assumeSym()
55 Loc::isLocType(SSE->getRHS()->getType())) { in assumeSym()
66 SymMgr.getSymSymExpr(SSE->getRHS(), BO_Sub, SSE->getLHS(), DiffTy); in assumeSym()
78 QualType ExprType = SSE->getType(); in assumeSym()
80 SymMgr.getSymSymExpr(SSE->getLHS(), BO_EQ, SSE->getRHS(), ExprType); in assumeSym()
82 bool WasEqual = SSE->getOpcode() == BO_EQ; in assumeSym()
H A DRangeConstraintManager.cpp1242 RangeSet VisitSymSymExpr(const SymSymExpr *SSE) { in VisitSymSymExpr() argument
1251 getRangeForNegatedSymSym(SSE), in VisitSymSymExpr()
1255 getRangeForComparisonSymbol(SSE), in VisitSymSymExpr()
1258 getRangeForEqualities(SSE), in VisitSymSymExpr()
1260 VisitBinaryOperator(SSE)); in VisitSymSymExpr()
1468 std::optional<RangeSet> getRangeForNegatedSymSym(const SymSymExpr *SSE) { in getRangeForNegatedSymSym() argument
1470 [SSE, State = this->State]() -> SymbolRef { in getRangeForNegatedSymSym()
1471 if (SSE->getOpcode() == BO_Sub) in getRangeForNegatedSymSym()
1473 SSE->getRHS(), BO_Sub, SSE->getLHS(), SSE->getType()); in getRangeForNegatedSymSym()
1476 SSE->getType()); in getRangeForNegatedSymSym()
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/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DLLVMContextImpl.cpp243 for (const auto &SSE : SSC) in getSyncScopeNames() local
244 SSNs[SSE.second] = SSE.first(); in getSyncScopeNames()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DX86.cpp1211 SSE, enumerator
1746 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp)) in postMerge()
1748 if (Hi == SSEUp && Lo != SSE) in postMerge()
1749 Hi = SSE; in postMerge()
1789 return SSE; in merge()
1819 Current = SSE; in classify()
1821 Lo = SSE; in classify()
1826 Lo = SSE; in classify()
1832 Current = SSE; in classify()
1907 Current = SSE; in classify()
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/freebsd/sys/contrib/openzfs/lib/libspl/include/sys/
H A Dsimd.h82 SSE = 0, enumerator
140 [SSE] = {1U, 0U, 1U << 25, EDX },
216 CPUID_FEATURE_CHECK(sse, SSE);
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterContext_x86.h328 SSE = FP << 1, enumerator
329 YMM = SSE << 1,
/freebsd/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DSMTConstraintManager.h288 if (const SymSymExpr *SSE = dyn_cast<SymSymExpr>(BSE)) in REGISTER_TRAIT_WITH_PROGRAMSTATE() local
289 return canReasonAbout(SVB.makeSymbolVal(SSE->getLHS())) && in REGISTER_TRAIT_WITH_PROGRAMSTATE()
290 canReasonAbout(SVB.makeSymbolVal(SSE->getRHS())); in REGISTER_TRAIT_WITH_PROGRAMSTATE()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td139 // In the case of SSE disabled --> save to stack
147 // In the case of SSE disabled --> save to stack
152 // In the case of SSE disabled --> save to stack
157 // In the case of SSE disabled --> save to stack
293 // Long double types are always returned in FP0 (even with SSE),
672 // If SSE was disabled, pass FP values smaller than 64-bits as integers in
763 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
779 // Other SSE vectors get 16-byte stack slots that are 4-byte aligned.
795 // SSE vector arguments are passed in XMM registers.
815 // SSE vector arguments are passed in XMM registers.
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H A DX86InstrInfo.td63 // SSE, MMX and 3DNow! vector support.
H A DX86InstrVecCompiler.td389 // movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2.
427 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
448 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
469 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
H A DX86InstrOperands.td388 // Unsigned immediate used by SSE/AVX instructions
433 // Unsigned 8-bit immediate used by SSE/AVX instructions.
449 // Used by some SSE/AVX instructions that use intrinsics.
H A DX86InstrUtils.td481 // SI - SSE 1 & 2 scalar instructions
498 // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512
514 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512
529 // PI - SSE 1 & 2 packed instructions
544 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
552 // PIi8 - SSE 1 & 2 packed instructions with immediate
712 // SS48I - SSE 4.1 instructions with T8 prefix.
713 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
726 // SS428I - SSE 4.2 instructions with T8 prefix.
732 // SS42AI = SSE 4.2 instructions with TA prefix
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H A DX86.td46 … "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)">;
70 "Enable SSE instructions">;
81 "Enable SSE 4.1 instructions",
84 "Enable SSE 4.2 instructions",
86 // The MMX subtarget feature is separate from the rest of the SSE features
88 // turn it off explicitly while allowing SSE+ to be on.
101 "Support SSE 4a instructions",
202 …"Allow unaligned memory operands with SSE instructions (this may require setting a configuration b…
468 // FIXME: This should not apply to CPUs that do not have SSE.
599 // using ymm/zmm registers before executing code that may use SSE instructions.
H A DX86ScheduleBtVer2.td54 // The Jaguar FP Retire Queue renames SIMD and FP uOps onto a pool of 72 SSE
58 // The PRF in the floating point unit can eliminate a move from a MMX or SSE
984 // SSE Zero-idioms.
1024 // SSE
1043 // SSE variants.
H A DX86InstrSSE.td1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
9 // This file describes the X86 SSE instruction set, defining the instructions,
16 // SSE 1 & 2 Instructions Classes
19 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
42 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
65 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
88 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
126 // AVX & SSE - Zero/One Vectors
185 // SSE 1 & 2 - Move FP Scalar Instructions
334 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
[all …]
H A DX86InstrFragmentsSIMD.td31 // SSE specific DAG Nodes.
813 // SSE pattern fragments
925 // memory operands in most SSE instructions, which are required to
1019 // Scalar SSE intrinsic fragments to match several different types of loads.
1020 // Used by scalar SSE intrinsic instructions which have 128 bit types, but
/freebsd/sys/contrib/openzfs/config/
H A Dtoolchain-simd.m440 AC_MSG_CHECKING([whether host toolchain supports SSE])
49 AC_DEFINE([HAVE_SSE], 1, [Define if host toolchain supports SSE])
/freebsd/sys/contrib/xen/arch-x86/
H A Dcpufeatureset.h117 XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DVFABIDemangling.cpp
/freebsd/sys/contrib/openzfs/module/
H A DKbuild.in261 # SSE register return with SSE disabled if -march=znverX is passed
/freebsd/sys/dev/aic7xxx/
H A Daic7xxx_pci.c664 #define SSE 0x40
2027 if (status1 & SSE) { in ahc_pci_intr()
2048 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { in ahc_pci_intr()
671 #define SSE global() macro
H A Daic79xx.reg1088 field SSE 0x40
1105 field SSE 0x40
1122 field SSE 0x40
1138 field SSE 0x40
1155 field SSE 0x40
1170 field SSE 0x40
1186 field SSE 0x40
H A Daic79xx_pci.c772 #define SSE 0x40 in ahd_configure_termination()
778 #define SSE global() macro
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DX86TargetParser.def144 X86_FEATURE_COMPAT(SSE, "sse", 2)
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod49 =item bit #0+25 denoting SSE support;

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