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Searched refs:LSU (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZEC12.td83 def : WriteRes<LSU, [ZEC12_LSUnit]>;
88 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
122 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
123 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
125 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCTH$")>;
126 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
127 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
132 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
146 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
154 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BRASL(_XPLINK64)?$")>;
[all …]
H A DSystemZScheduleZ196.td82 def : WriteRes<LSU, [Z196_LSUnit]>;
87 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
116 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
117 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
118 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
119 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
120 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCT(G|H)?$")>;
121 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
122 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
126 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
[all …]
H A DSystemZScheduleZ16.td88 def : WriteRes<LSU, [Z16_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z16_LSUnit]>;
141 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
163 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
185 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
200 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
202 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
[all …]
H A DSystemZScheduleZ15.td88 def : WriteRes<LSU, [Z15_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
140 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
163 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
185 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
200 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
202 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
[all …]
H A DSystemZScheduleZ13.td88 def : WriteRes<LSU, [Z13_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
162 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
183 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
197 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
198 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
200 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
210 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;
[all …]
H A DSystemZScheduleZ14.td88 def : WriteRes<LSU, [Z14_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
140 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
163 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
185 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
198 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
199 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
200 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
[all …]
H A DSystemZSchedule.td22 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
29 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
43 def "LSU"#Num : SchedWrite;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSyntacoreSCR3.td64 multiclass SCR3_Memory<ProcResourceKind LSU> {
66 def : WriteRes<WriteSTB, [LSU]>;
67 def : WriteRes<WriteSTH, [LSU]>;
68 def : WriteRes<WriteSTW, [LSU]>;
69 def : WriteRes<WriteSTD, [LSU]>;
70 def : WriteRes<WriteLDB, [LSU]>;
71 def : WriteRes<WriteLDH, [LSU]>;
72 def : WriteRes<WriteLDW, [LSU]>;
73 def : WriteRes<WriteLDD, [LSU]>;
78 multiclass SCR3_AtomicMemory<ProcResourceKind LSU> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp55 LSUnit::Status LSS = LSU.isAvailable(IR); in isAvailable()
67 llvm_unreachable("Don't know how to process this LSU state result!"); in isAvailable()
87 LSU.onInstructionIssued(IR); in issueInstructionImpl()
88 const MemoryGroup &Group = LSU.getGroup(IS->getLSUTokenID()); in issueInstructionImpl()
95 LSU.onInstructionExecuted(IR); in issueInstructionImpl()
106 HasDependentUsers |= Inst.isMemOp() && LSU.hasDependentUsers(IR); in issueInstruction()
135 if (IS.isMemOp() && !LSU.isReady(IR)) { in promoteToReadySet()
172 if (IS.isMemOp() && LSU.isWaiting(IR)) { in promoteToPendingSet()
233 LSU.onInstructionExecuted(IR); in updateIssuedSet()
256 if (IS.isMemOp() && LSU in analyzeDataDependencies()
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/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DContext.cpp42 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, in createDefaultPipeline() local
44 auto HWS = std::make_unique<Scheduler>(SM, *LSU); in createDefaultPipeline()
52 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); in createDefaultPipeline()
57 addHardwareUnit(std::move(LSU)); in createDefaultPipeline()
77 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, in createInOrderPipeline() local
82 auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU); in createInOrderPipeline()
87 addHardwareUnit(std::move(LSU)); in createInOrderPipeline()
/freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp48 LSUnit &LSU) in InOrderIssueStage() argument
49 : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU), in InOrderIssueStage()
129 if (IR.getInstruction()->isMemOp() && !LSU.isReady(IR)) { in canExecute()
201 IS.setLSUTokenID(LSU.dispatch(IR)); in execute()
238 LSU.onInstructionIssued(IR); in tryIssue()
265 LSU.onInstructionExecuted(IR); in tryIssue()
302 LSU.onInstructionExecuted(IR); in updateIssuedInst()
342 LSU.onInstructionExecuted(CarriedOver); in updateCarriedOver()
361 LSU.onInstructionRetired(IR); in retireInstruction()
402 LSU.cycleEvent(); in cycleStart()
H A DRetireStage.cpp67 LSU.onInstructionRetired(IR); in notifyInstructionRetired()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DRetireStage.h32 LSUnitBase &LSU; variable
39 : RCU(R), PRF(F), LSU(LS) {} in RetireStage()
H A DInOrderIssueStage.h59 LSUnit &LSU; variable
116 CustomBehaviour &CB, LSUnit &LSU);
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DScheduler.h71 LSUnitBase &LSU; variable
167 : LSU(Lsu), Resources(std::move(RM)), BusyResourceUnits(0), in Scheduler()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP7.td145 // Instructions of LSU and FXU pipelines
H A DPPCScheduleP8.td
H A DPPCScheduleE500.td25 // 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
31 def E500_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCScheduleE500mc.td25 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
35 def E500mc_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCScheduleE5500.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
38 def E5500_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCInstrInfo.td2534 /// that they will fill slots (which could cause the load of a LSU reject to
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedOryon.td37 // LSU has 4 ports p6 ~ p9(ls0 ~ ls3), p10/p11(std0, std1) has to work with ls0~ls3
40 // cross IXU/LSU/VXU resource group for FMOV P41 of VXU
195 // cross IXU/LSU/VXU resource group for FMOV P41 of VXU
349 // LSU resource definition
861 // Instruction Tables in LSU