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Searched refs:CLK_TOP_UNIVPLL2_D4 (Results 1 – 16 of 16) sorted by relevance

/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h33 #define CLK_TOP_UNIVPLL2_D4 26 macro
H A Dmt8135-clk.h49 #define CLK_TOP_UNIVPLL2_D4 38 macro
H A Dmt7629-clk.h55 #define CLK_TOP_UNIVPLL2_D4 45 macro
H A Dmt7622-clk.h49 #define CLK_TOP_UNIVPLL2_D4 37 macro
H A Dmt6797-clk.h73 #define CLK_TOP_UNIVPLL2_D4 63 macro
H A Dmediatek,mt6795-clk.h76 #define CLK_TOP_UNIVPLL2_D4 65 macro
H A Dmt8173-clk.h78 #define CLK_TOP_UNIVPLL2_D4 68 macro
H A Dmt6765-clk.h62 #define CLK_TOP_UNIVPLL2_D4 27 macro
H A Dmediatek,mt8365-clk.h37 #define CLK_TOP_UNIVPLL2_D4 27 macro
H A Dmt2712-clk.h62 #define CLK_TOP_UNIVPLL2_D4 31 macro
H A Dmt2701-clk.h40 #define CLK_TOP_UNIVPLL2_D4 30 macro
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-slave-mt27xx.txt20 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
H A Dspi-mt65xx.txt34 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7629.dtsi253 <&topckgen CLK_TOP_UNIVPLL2_D4>;
323 <&topckgen CLK_TOP_UNIVPLL2_D4>,
390 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt2712e.dtsi556 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
635 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
648 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
661 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
674 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
H A Dmt8365.dtsi619 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,