Searched refs:CLK_TOP_UNIVPLL1_D2 (Results 1 – 14 of 14) sorted by relevance
17 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.32 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;324 <&topckgen CLK_TOP_UNIVPLL1_D2>;392 <&topckgen CLK_TOP_UNIVPLL1_D2>;468 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
29 #define CLK_TOP_UNIVPLL1_D2 22 macro
43 #define CLK_TOP_UNIVPLL1_D2 32 macro
50 #define CLK_TOP_UNIVPLL1_D2 40 macro
44 #define CLK_TOP_UNIVPLL1_D2 32 macro
68 #define CLK_TOP_UNIVPLL1_D2 58 macro
71 #define CLK_TOP_UNIVPLL1_D2 60 macro
73 #define CLK_TOP_UNIVPLL1_D2 63 macro
58 #define CLK_TOP_UNIVPLL1_D2 23 macro
33 #define CLK_TOP_UNIVPLL1_D2 23 macro
57 #define CLK_TOP_UNIVPLL1_D2 26 macro
36 #define CLK_TOP_UNIVPLL1_D2 26 macro
322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;