Home
last modified time | relevance | path

Searched +full:zynq +full:- +full:devcfg +full:- +full:1 (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dxilinx-zynq-fpga-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq FPGA Manager
10 - Michal Simek <michal.simek@amd.com>
14 const: xlnx,zynq-devcfg-1.0
17 maxItems: 1
20 maxItems: 1
23 maxItems: 1
[all …]
H A Dfpga-region.txt6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
82 ---
[all...]
/freebsd/share/man/man4/man4.arm/
H A Ddevcfg.48 .\" 1. Redistributions of source code must retain the above copyright
29 .Nm devcfg
30 .Nd Zynq PL device config interface
32 .Cd device devcfg
35 .Pa /dev/devcfg
36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
41 asserts the top-level PL reset signals, disables the PS-PL level shifters,
44 When the PL asserts the DONE signal, the devcfg driver will enable the level
45 shifters and release the top-level PL reset signals.
49 .Bd -literal -offset indent
[all …]
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_devcfg.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section
31 * of Zynq.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
88 #define DEVCFG_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
89 #define DEVCFG_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
91 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
93 #define DEVCFG_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx);
[all …]
H A Dzy7_slcr.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
66 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
67 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
69 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
71 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
[all …]
/freebsd/sys/dts/arm/
H A Dzynq-7000.dtsi1 /*-
8 * 1. Redistributions of source code must retain the above copyright
29 compatible = "xlnx,zynq-7000";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 interrupt-parent = <&GIC>;
38 // Zynq PS System registers.
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
[all …]