Lines Matching +full:zynq +full:- +full:devcfg +full:- +full:1

1 /*-
8  * 1. Redistributions of source code must retain the above copyright
29 	compatible = "xlnx,zynq-7000";
30 	#address-cells = <1>;
31 	#size-cells = <1>;
32 	interrupt-parent = <&GIC>;
38 	// Zynq PS System registers.
42 		compatible = "simple-bus";
43 		#address-cells = <1>;
44 		#size-cells = <1>;
56 			interrupt-controller;
57 			#address-cells = <0>;
58 			#interrupt-cells = <3>;
68 			interrupt-parent = <&GIC>;
72 		devcfg: devcfg@7000 {  label
76 			interrupt-parent = <&GIC>;
79 		// triple timer counters0,1
92 			compatible = "arm,mpcore-timers";
93 			#address-cells = <1>;
94 			#size-cells = <0>;
97 			interrupts = <1 11 1>, <1 13 1>;
98 			interrupt-parent = <&GIC>;
101 		// system watch-dog timer
106 		 	interrupts = <0 9 1>;
107 		 	interrupt-parent = <&GIC>;
114 		 	interrupts = <1 14 1>;
115 		 	interrupt-parent = <&GIC>;
116 		 	reset = <1>;
121 	// Zynq PS I/O Peripheral registers.
125 		compatible = "simple-bus";
126 		#address-cells = <1>;
127 		#size-cells = <1>;
137 			interrupt-parent = <&GIC>;
138 			clock-frequency = <50000000>;
147 			interrupt-parent = <&GIC>;
148 			clock-frequency = <50000000>;
157 			interrupt-parent = <&GIC>;
165 			interrupt-parent = <&GIC>;
173 		 	interrupt-parent = <&GIC>;
179 			compatible = "cdns,zynq-gem", "cadence,gem";
183 			interrupt-parent = <&GIC>;
184 			ref-clock-num = <0>;
189 			compatible = "cdns,zynq-gem", "cadence,gem";
193 			interrupt-parent = <&GIC>;
194 			ref-clock-num = <1>;
197 		// Quad-SPI controller
203 			interrupt-parent = <&GIC>;
204 			ref-clock = <200000000>; // 200 Mhz
205 			spi-clock = <50000000>;  // 50 Mhz
214 			interrupt-parent = <&GIC>;
222 			interrupt-parent = <&GIC>;
231 			interrupt-parent = <&GIC>;
232 			max-frequency = <50000000>;
240 			interrupt-parent = <&GIC>;
241 			max-frequency = <50000000>;