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/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <tjeznach@rivosinc.com>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
20 interrupt or MSI notifications.
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-v3s-anbernic-rg-nano.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include "sun8i-v3s.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s";
19 compatible = "pwm-backlight";
20 brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>;
21 default-brightness-level = <11>;
22 power-supply = <&reg_vcc5v0>;
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dst-rc.txt1 Device-Tree bindings for ST IRB IP
4 - compatible: Should contain "st,comms-irb".
5 - reg: Base physical address of the controller and length of memory
7 - interrupts: interrupt-specifier for the sole interrupt generated by
8 the device. The interrupt specifier format depends on the interrupt
10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
11 protocol used for receiving remote control signals. rx-mode should
12 be present iff the rx pins are wired up.
13 - tx-mode: should be "infrared". This property specifies the L1
14 protocol used for transmitting remote control signals. tx-mode should
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-href-tvk1281618-r2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "gpio-keys";
12 #address-cells = <1>;
13 #size-cells = <0>;
14 vdd-supply = <&ab8500_ldo_aux1_reg>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
37 interrupt-parent = <&gpio6>;
[all …]
/linux/Documentation/scsi/
H A D53c700.rst1 .. SPDX-License-Identifier: GPL-2.0
10 This driver supports the 53c700 and 53c700-66 chips. It also supports
12 does sync (-66 and 710 only), disconnects and tag command queueing.
37 driver, you need to know three things about the way the chip is wired
41 2. The interrupt line used
45 the SCSI Id from the card bios or whether the chip is wired for
62 53c700-66 50MHz
77 routine into the interrupt line and call NCR_700_detect with the host
84 interrupt.
87 -------------------
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmti,cpu-interrupt-controller.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS CPU Interrupt Controller
13 With the irq_domain in place we can describe how the 8 IRQs are wired to the
14 platforms internal interrupt controller cascade.
17 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
21 const: mti,cpu-interrupt-controller
23 '#interrupt-cells':
[all …]
H A Dmarvell,ap806-sei.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-sei.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell SEI (System Error Interrupt) Controller
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It
15 interrupt line (an SPI) on the parent interrupt controller.
17 This interrupt controller can handle up to 64 SEIs, a set comes from the AP
18 and is wired while a second set comes from the CPs by the mean of MSIs.
[all …]
H A Dmarvell,mpic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
16 On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
26 - description: main registers
[all …]
H A Dbrcm,bcm6345-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6345-style Level 1 interrupt controller
10 - Simon Arlott <simon@octiron.net>
13 This block is a first level interrupt controller that is typically connected
18 - 32, 64 or 128 incoming level IRQ lines
20 - Most onchip peripherals are wired directly to an L1 input
22 - A separate instance of the register set for each CPU, allowing individual
[all …]
H A Darm,vic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Vectored Interrupt Controller
10 - Rob Herring <robh@kernel.org>
13 One or more Vectored Interrupt Controllers (VIC's) can be connected in an
14 ARM system for interrupt routing. For multiple controllers they can either
15 be nested or have the outputs wire-OR'd together.
18 - $ref: /schemas/interrupt-controller.yaml#
[all …]
H A Dmarvell,ap806-gicp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-gicp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
15 located in the Marvell CP110 to turn wired interrupts inside the CP
20 const: marvell,ap806-gicp
25 marvell,spi-ranges:
26 description: Tuples of GIC SPI interrupt ranges available for this GICP
27 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
H A Dbrcm,bcm7038-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
10 This block is a first level interrupt controller that is typically connected
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
[all …]
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller is a simple interrupt controller present on
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
[all …]
/linux/arch/mips/kvm/
H A Dvz.c31 #include "interrupt.h"
115 if (kvm_mips_guest_has_msa(&vcpu->arch)) in kvm_vz_config5_guest_wrmask()
122 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { in kvm_vz_config5_guest_wrmask()
140 * Config1: M, [MMUSize-1, C2, MD, PC, WR, CA], FP
158 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) in kvm_vz_config1_user_wrmask()
175 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) in kvm_vz_config3_user_wrmask()
205 set_bit(priority, &vcpu->arch.pending_exceptions); in kvm_vz_queue_irq()
206 clear_bit(priority, &vcpu->arch.pending_exceptions_clr); in kvm_vz_queue_irq()
211 clear_bit(priority, &vcpu->arch.pending_exceptions); in kvm_vz_dequeue_irq()
212 set_bit(priority, &vcpu->arch.pending_exceptions_clr); in kvm_vz_dequeue_irq()
[all …]
/linux/drivers/irqchip/
H A Dirq-al-fic.c1 // SPDX-License-Identifier: GPL-2.0
28 MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
58 gc->chip_types->handler = handler; in al_fic_set_trigger()
59 fic->state = new_state; in al_fic_set_trigger()
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
66 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
69 guard(raw_spinlock)(&gc->lock); in al_fic_irq_set_type()
74 return -EINVAL; in al_fic_irq_set_type()
82 * This is generally fixed depending on what pieces of HW it's wired up in al_fic_irq_set_type()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-tx6ul-mainboard.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6ul-tx6ul.dtsi"
11 model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
12 compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
15 lcdif-24bit-pins-a = &pinctrl_disp0_3;
17 /delete-property/ mmc1;
21 /delete-node/ sound;
25 xceiver-supply = <&reg_3v3>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dwiznet,w5x00.txt9 - compatible: Should be one of the following strings:
13 - reg: Specify the SPI chip select the chip is wired to.
14 - interrupts: Specify the interrupt index within the interrupt controller (referred
15 to above in interrupt-parent) and interrupt type. w5x00 natively
18 - pinctrl-names: List of assigned state names, see pinctrl binding documentation.
19 - pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
24 - spi-max-frequency: Maximum frequency of the SPI bus when accessing the w5500.
27 - local-mac-address: See ethernet.txt in the same directory.
36 pinctrl-names = "default";
37 pinctrl-0 = <&eth1_pins>;
[all …]
H A Dmicrochip,enc28j60.txt9 - compatible: Should be "microchip,enc28j60"
10 - reg: Specify the SPI chip select the ENC28J60 is wired to
11 - interrupts: Specify the interrupt index within the interrupt controller (referred
12 to above in interrupt-parent) and interrupt type. The ENC28J60 natively
15 - pinctrl-names: List of assigned state names, see pinctrl binding documentation.
16 - pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
21 - spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60.
31 compatible = "fsl,imx28-spi";
32 pinctrl-names = "default";
33 pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>;
[all …]
/linux/Documentation/hwmon/
H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
36 Override the BIOS default temperature interrupt mode.
37 The only possible value is 0 which forces interrupt
38 mode 0. In this mode, any pending interrupt is cleared
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dx-powers,axp152.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/x-powers,axp152.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: X-Powers AXP PMIC
10 - Chen-Yu Tsai <wens@csie.org>
13 - if:
18 - x-powers,axp152
19 - x-powers,axp202
20 - x-powers,axp209
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Denvelope-detector.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/envelope-detector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
14 signal by a binary search using the output of a comparator wired to
15 an interrupt pin. Like so:
18 input +------>-------|+ \
20 .-------. | }---.
22 | dac|-->--|- / |
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-adc-envelope-detector8 of a comparator wired to an interrupt pin. Like so::
12 input +------>-------|+ \
14 .-------. | }---.
16 | dac|-->--|- / |
20 | irq|------<-------'
22 '-------'
29 The edge/level of the interrupt is also switched to its
/linux/Documentation/devicetree/bindings/input/
H A Delan,ekth6915.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Elan I2C-HID touchscreen controllers
10 - Douglas Anderson <dianders@chromium.org>
13 Supports the Elan eKTH6915 and other I2C-HID touchscreen controllers.
14 These touchscreen controller use the i2c-hid protocol with a reset GPIO.
17 - $ref: /schemas/input/touchscreen/touchscreen.yaml#
22 - items:
23 - enum:
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h618-orangepi-zero3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-h616-orangepi-zero.dtsi"
9 #include "sun50i-h616-cpu-opp.dtsi"
13 compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
17 cpu-supply = <&reg_dcdc2>;
21 allwinner,tx-delay-ps = <700>;
22 phy-mode = "rgmii-rxid";
23 phy-supply = <&reg_dldo1>;
27 motorcomm,clk-out-frequency-hz = <125000000>;
[all …]

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