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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
[all …]
/linux/drivers/pwm/
H A Dpwm-adp5585.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * - The .apply() operation executes atomically, but may not wait for the
11 * - Disabling the PWM drives the output pin to a low level immediately.
12 * - The hardware can only generate normal polarity output.
52 /* Configure the R3 pin as PWM output. */ in pwm_adp5585_request()
53 return regmap_update_bits(adp5585_pwm->regmap, adp5585_pwm->ext_cfg, in pwm_adp5585_request()
62 regmap_update_bits(adp5585_pwm->regmap, adp5585_pwm->ext_cfg, in pwm_adp5585_free()
72 const struct adp5585_pwm_chip *info = adp5585_pwm->info; in pwm_adp5585_apply()
73 struct regmap *regmap = adp5585_pwm->regmap; in pwm_adp5585_apply()
79 if (!state->enabled) { in pwm_adp5585_apply()
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/linux/include/linux/
H A Dwm97xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
62 #define WM97XX_SLT(i) ((i - 5) & 0x7) /* panel slot (5-11) */
71 #define WM9712_45W 0x1000 /* set for 5-wire touchscreen */
73 #define WM9712_WAIT 0x0200 /* wait until adc is read before next sample */
75 #define WM9712_MASK_HI 0x0040 /* hi on mask pin (47) stops conversions */
76 #define WM9712_MASK_EDGE 0x0080 /* rising/falling edge on pin delays sample */
90 #define WM9705_WAIT 0x0100 /* wait until adc is read before next sample */
94 #define WM9705_MASK_EDGE 0x0020 /* rising/falling edge on pin delays sample */
100 #define WM9713_PDPOL 0x0400 /* Pen down polarity */
110 #define WM9713_WAIT 0x0200 /* coordinate wait */
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/linux/arch/m68k/include/asm/
H A DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
[all …]
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
[all …]
H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
138 #define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8) argument
235 u32 pin; member
236 u32 polarity; member
258 /* Define chip-selects as reserved by default until probe completes */
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/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l36.txt5 - compatible : "cirrus,cs35l36"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
18 - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
24 - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value.
32 - cirrus,multi-amp-mode : Boolean to determine if there are more than
33 one amplifier in the system. If more than one it is best to Hi-Z the ASP
36 - cirrus,boost-ctl-select : Boost converter control source selection.
39 0x00 - Control Port Value
[all …]
/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
136 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
139 /* Wait pin polarity values */
153 bool wait_on_read; /* monitor wait on reads */
[all …]
/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
99 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
100 #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
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/linux/Documentation/devicetree/bindings/input/
H A Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 - $ref: input.yaml#
16 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
17 additional Hall-effect and inductive sensing capabilities.
24 - azoteq,iqs269a
25 - azoteq,iqs269a-00
26 - azoteq,iqs269a-d0
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H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
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/linux/drivers/extcon/
H A Dextcon-usbc-tusb320.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/extcon/extcon-tusb320.c - TUSB320 extcon driver
10 #include <linux/extcon-provider.h>
108 ret = regmap_read(priv->regmap, sizeof(sig) - 1 - i, &val); in tusb320_check_signature()
112 dev_err(priv->dev, "signature mismatch!\n"); in tusb320_check_signature()
113 return -ENODEV; in tusb320_check_signature()
125 if (priv->state != TUSB320_ATTACHED_STATE_NONE) in tusb320_set_mode()
126 return -EBUSY; in tusb320_set_mode()
129 ret = regmap_write_bits(priv->regmap, TUSB320_REGA, in tusb320_set_mode()
133 dev_err(priv->dev, "failed to write mode: %d\n", ret); in tusb320_set_mode()
[all …]
/linux/drivers/input/touchscreen/
H A Dpixcir_i2c_ts.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Pixcir, Inc.
34 * using the RESET pin.
65 * struct pixcir_i2c_chip_data - chip related data
102 const struct pixcir_i2c_chip_data *chip = tsdata->chip; in pixcir_ts_parse()
106 i = chip->has_hw_ids ? 1 : 0; in pixcir_ts_parse()
107 readsize = 2 + tsdata->chip->max_fingers * (4 + i); in pixcir_ts_parse()
111 ret = i2c_master_send(tsdata->client, wrbuf, sizeof(wrbuf)); in pixcir_ts_parse()
113 dev_err(&tsdata->client->dev, in pixcir_ts_parse()
119 ret = i2c_master_recv(tsdata->client, rdbuf, readsize); in pixcir_ts_parse()
[all …]
/linux/arch/x86/kernel/apic/
H A Dio_apic.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75 #define for_each_pin(idx, pin) \ argument
76 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
77 #define for_each_ioapic_pin(idx, pin) \ argument
[all …]
/linux/drivers/watchdog/
H A Dsmsc37b787_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * any of this software. This material is provided "AS-IS" in
12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>
15 * 2003 - Created version 1.0 for Linux 2.4.x.
16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
29 * that everything is in order, and that the watchdog should wait
38 * For an example userspace keep-alive daemon, see:
86 /* -- Low level function ----------------------------------------*/
124 /* -- Medium level functions ------------------------------------*/
128 /* -- General Purpose I/O Bit 1.2 -- in gpio_bit12()
[all …]
/linux/drivers/spi/
H A Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
30 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
31 #define RSPI_SPPCR 0x02 /* Pin Control Register */
40 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
68 /* SPCR - Control Register */
77 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78 /* QSPI on R-Car Gen2 only */
79 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-pinephone-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf
12 /dts-v1/;
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/input/linux-event-codes.h>
15 #include <dt-bindings/leds/common.h>
16 #include "rk3399-s.dtsi"
20 compatible = "pine64,pinephone-pro", "rockchip,rk3399";
21 chassis-type = "handset";
30 stdout-path = "serial2:115200n8";
[all …]
/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
91 * Controller (UDC) Control/Status register end-point 0
94 * Controller (UDC) Control/Status register end-point 1
97 * Controller (UDC) Control/Status register end-point 2
100 * Controller (UDC) Data register end-point 0
[all …]
/linux/drivers/comedi/drivers/
H A Dcb_pcimdas.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Comedi driver for Computer Boards PCIM-DAS1602/16 and PCIe-DAS1602/16
6 * COMEDI - Linux Control and Measurement Device Interface
13 * Devices: [ComputerBoards] PCIM-DAS1602/16 (cb_pcimdas), PCIe-DAS1602/16
18 * Written to support the PCIM-DAS1602/16 and PCIe-DAS1602/16.
31 * https://www.mccdaq.com/PDFs/Manuals/pcim-das1602-16.pdf
32 * https://www.mccdaq.com/PDFs/Manuals/pcie-das1602-16.pdf
49 * PCI Bar 2 Register map (devpriv->daqio)
56 * PCI Bar 3 Register map (devpriv->BADR3)
107 * PCI Bar 4 Register map (dev->iobase)
[all …]
H A Ds626.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
163 * GPIO2 input pin: 0=AdcBusy,
180 * Shut down all MC1-controlled
231 #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */
232 #define S626_P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
44 #define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */
45 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
192 /* Defined polarity of Dock/Undock indication in SDP[0] */
[all …]
/linux/drivers/bluetooth/
H A Dhci_bcm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
53 * struct bcm_device_data - device specific data
55 * @drive_rts_on_open: drive RTS signal on ->open() when platform requires it
69 * struct bcm_device - device driver resources
74 * @device_wakeup: BT_WAKE pin,
77 * @shutdown: BT_REG_ON pin,
79 * @reset: BT_RST_N pin,
81 * @set_device_wakeup: callback to toggle BT_WAKE pin
83 * @set_shutdown: callback to toggle BT_REG_ON pin
85 * @btlp: Apple ACPI method to toggle BT_WAKE pin ("Bluetooth Low Power")
[all …]
/linux/drivers/usb/typec/tcpm/
H A Dfusb302.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
42 * longer than PD_T_PD_DEBPUNCE (10-20ms).
131 return chip->logbuffer_tail == in fusb302_log_full()
132 (chip->logbuffer_head + 1) % LOG_BUFFER_ENTRIES; in fusb302_log_full()
143 if (!chip->logbuffer[chip->logbuffer_head]) { in _fusb302_log()
144 chip->logbuffer[chip->logbuffer_head] = in _fusb302_log()
146 if (!chip->logbuffer[chip->logbuffer_head]) in _fusb302_log()
152 mutex_lock(&chip->logbuffer_lock); in _fusb302_log()
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/linux/drivers/net/ethernet/smsc/
H A Dsmc91x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*------------------------------------------------------------------------
3 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
21 ---------------------------------------------------------------------------*/
29 * Any 16-bit access is performed with two 8-bit accesses if the hardware
30 * can't do it directly. Most registers are 16-bit so those are mandatory.
55 #include <asm/mach-types.h>
65 #define SMC_IO_SHIFT (lp->io_shift)
96 #define SMC_IRQ_FLAGS (-1) /* from resource */
114 (lp)->cfg.pxa_u16_align4)
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