Lines Matching +full:wait +full:- +full:pin +full:- +full:polarity
1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75 #define for_each_pin(idx, pin) \ argument
76 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
77 #define for_each_ioapic_pin(idx, pin) \ argument
79 for_each_pin((idx), (pin))
90 int apic, pin; member
110 /* Saved state during suspend/resume, or while enabling intr-remap. */
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
145 static inline u32 mp_pin_to_gsi(int ioapic, int pin) in mp_pin_to_gsi() argument
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
180 * disable_ioapic_support() - disables ioapic support at runtime
186 noioapicreroute = -1; in disable_ioapic_support()
193 /* disable IO-APIC */ in parse_noapic()
205 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, in mp_save_irq()
206 m->srcbusirq, m->dstapic, m->dstirq); in mp_save_irq()
268 writel(vector, &io_apic->eoi); in io_apic_eoi()
275 writel(reg, &io_apic->index); in native_io_apic_read()
276 return readl(&io_apic->data); in native_io_apic_read()
284 writel(reg, &io_apic->index); in io_apic_write()
285 writel(value, &io_apic->data); in io_apic_write()
288 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) in __ioapic_read_entry() argument
292 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin); in __ioapic_read_entry()
293 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin); in __ioapic_read_entry()
298 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) in ioapic_read_entry() argument
301 return __ioapic_read_entry(apic, pin); in ioapic_read_entry()
310 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) in __ioapic_write_entry() argument
312 io_apic_write(apic, 0x11 + 2*pin, e.w2); in __ioapic_write_entry()
313 io_apic_write(apic, 0x10 + 2*pin, e.w1); in __ioapic_write_entry()
316 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) in ioapic_write_entry() argument
319 __ioapic_write_entry(apic, pin, e); in ioapic_write_entry()
327 static void ioapic_mask_entry(int apic, int pin) in ioapic_mask_entry() argument
332 io_apic_write(apic, 0x10 + 2*pin, e.w1); in ioapic_mask_entry()
333 io_apic_write(apic, 0x11 + 2*pin, e.w2); in ioapic_mask_entry()
337 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
338 * shared ISA-space IRQs, so we have to support them. We are super
339 * fast in the common case, and fast for shared ISA-space IRQs.
341 static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin) in add_pin_to_irq_node() argument
346 for_each_irq_pin(entry, data->irq_2_pin) { in add_pin_to_irq_node()
347 if (entry->apic == apic && entry->pin == pin) in add_pin_to_irq_node()
353 pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin); in add_pin_to_irq_node()
357 entry->apic = apic; in add_pin_to_irq_node()
358 entry->pin = pin; in add_pin_to_irq_node()
359 list_add_tail(&entry->list, &data->irq_2_pin); in add_pin_to_irq_node()
363 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) in __remove_pin_from_irq() argument
367 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) { in __remove_pin_from_irq()
368 if (entry->apic == apic && entry->pin == pin) { in __remove_pin_from_irq()
369 list_del(&entry->list); in __remove_pin_from_irq()
381 data->entry.masked = masked; in io_apic_modify_irq()
383 for_each_irq_pin(entry, data->irq_2_pin) { in io_apic_modify_irq()
384 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1); in io_apic_modify_irq()
391 * Synchronize the IO-APIC and the CPU by doing a dummy read from the
392 * IO-APIC
398 io_apic = io_apic_base(entry->apic); in io_apic_sync()
399 readl(&io_apic->data); in io_apic_sync()
404 struct mp_chip_data *data = irq_data->chip_data; in mask_ioapic_irq()
417 struct mp_chip_data *data = irq_data->chip_data; in unmask_ioapic_irq()
424 * IO-APIC versions below 0x20 don't support EOI register.
429 * 30h-FFh Reserved
431 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
433 * use io-apic's of version 0x20.
435 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
439 static void __eoi_ioapic_pin(int apic, int pin, int vector) in __eoi_ioapic_pin() argument
446 entry = entry1 = __ioapic_read_entry(apic, pin); in __eoi_ioapic_pin()
452 __ioapic_write_entry(apic, pin, entry1); in __eoi_ioapic_pin()
455 __ioapic_write_entry(apic, pin, entry); in __eoi_ioapic_pin()
464 for_each_irq_pin(entry, data->irq_2_pin) in eoi_ioapic_pin()
465 __eoi_ioapic_pin(entry->apic, entry->pin, vector); in eoi_ioapic_pin()
468 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) in clear_IO_APIC_pin() argument
472 /* Check delivery_mode to be sure we're not clearing an SMI pin */ in clear_IO_APIC_pin()
473 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
478 * Make sure the entry is masked and re-read the contents to check in clear_IO_APIC_pin()
479 * if it is a level triggered pin and if the remote-IRR is set. in clear_IO_APIC_pin()
483 ioapic_write_entry(apic, pin, entry); in clear_IO_APIC_pin()
484 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
490 * doesn't clear the remote-IRR if the trigger mode is not in clear_IO_APIC_pin()
495 ioapic_write_entry(apic, pin, entry); in clear_IO_APIC_pin()
498 __eoi_ioapic_pin(apic, pin, entry.vector); in clear_IO_APIC_pin()
502 * Clear the rest of the bits in the IO-APIC RTE except for the mask in clear_IO_APIC_pin()
505 ioapic_mask_entry(apic, pin); in clear_IO_APIC_pin()
506 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
508 pr_err("Unable to reset IRR for apic: %d, pin :%d\n", in clear_IO_APIC_pin()
509 mpc_ioapic_id(apic), pin); in clear_IO_APIC_pin()
514 int apic, pin; in clear_IO_APIC() local
516 for_each_ioapic_pin(apic, pin) in clear_IO_APIC()
517 clear_IO_APIC_pin(apic, pin); in clear_IO_APIC()
522 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
523 * specific CPU-side IRQs.
528 [0 ... MAX_PIRQS - 1] = -1
537 apic_pr_verbose("PIRQ redirection, working around broken MP-BIOS.\n"); in ioapic_pirq_setup()
544 apic_pr_verbose("... PIRQ%d -> IRQ %d\n", i, ints[i + 1]); in ioapic_pirq_setup()
546 pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; in ioapic_pirq_setup()
554 * Saves all the IO-APIC RTE's
558 int apic, pin; in save_ioapic_entries() local
563 err = -ENOMEM; in save_ioapic_entries()
567 for_each_pin(apic, pin) in save_ioapic_entries()
568 ioapics[apic].saved_registers[pin] = ioapic_read_entry(apic, pin); in save_ioapic_entries()
579 int apic, pin; in mask_ioapic_entries() local
585 for_each_pin(apic, pin) { in mask_ioapic_entries()
588 entry = ioapics[apic].saved_registers[pin]; in mask_ioapic_entries()
591 ioapic_write_entry(apic, pin, entry); in mask_ioapic_entries()
602 int apic, pin; in restore_ioapic_entries() local
608 for_each_pin(apic, pin) in restore_ioapic_entries()
609 ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]); in restore_ioapic_entries()
615 * Find the IRQ entry number of a certain pin.
617 static int find_irq_entry(int ioapic_idx, int pin, int type) in find_irq_entry() argument
625 mp_irqs[i].dstirq == pin) in find_irq_entry()
629 return -1; in find_irq_entry()
633 * Find the pin to which IRQ[irq] (ISA) is connected
646 return -1; in find_isa_irq_pin()
670 return -1; in find_isa_irq_apic()
678 * Determine IRQ line polarity (high active or low active): in irq_active_low()
683 * Conforms to spec, ie. bus-type dependent polarity. PCI in irq_active_low()
690 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n"); in irq_active_low()
748 * Conforms to spec, ie. bus-type dependent trigger in irq_is_level()
765 static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity) in __acpi_get_override_irq() argument
767 int ioapic, pin, idx; in __acpi_get_override_irq() local
770 return -1; in __acpi_get_override_irq()
774 return -1; in __acpi_get_override_irq()
776 pin = mp_find_ioapic_pin(ioapic, gsi); in __acpi_get_override_irq()
777 if (pin < 0) in __acpi_get_override_irq()
778 return -1; in __acpi_get_override_irq()
780 idx = find_irq_entry(ioapic, pin, mp_INT); in __acpi_get_override_irq()
782 return -1; in __acpi_get_override_irq()
785 *polarity = irq_active_low(idx); in __acpi_get_override_irq()
799 int trigger, int polarity) in ioapic_set_alloc_attr() argument
802 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; in ioapic_set_alloc_attr()
803 info->ioapic.node = node; in ioapic_set_alloc_attr()
804 info->ioapic.is_level = trigger; in ioapic_set_alloc_attr()
805 info->ioapic.active_low = polarity; in ioapic_set_alloc_attr()
806 info->ioapic.valid = 1; in ioapic_set_alloc_attr()
811 u32 gsi, int ioapic_idx, int pin) in ioapic_copy_alloc_attr() argument
816 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; in ioapic_copy_alloc_attr()
817 dst->devid = mpc_ioapic_id(ioapic_idx); in ioapic_copy_alloc_attr()
818 dst->ioapic.pin = pin; in ioapic_copy_alloc_attr()
819 dst->ioapic.valid = 1; in ioapic_copy_alloc_attr()
820 if (src && src->ioapic.valid) { in ioapic_copy_alloc_attr()
821 dst->ioapic.node = src->ioapic.node; in ioapic_copy_alloc_attr()
822 dst->ioapic.is_level = src->ioapic.is_level; in ioapic_copy_alloc_attr()
823 dst->ioapic.active_low = src->ioapic.active_low; in ioapic_copy_alloc_attr()
825 dst->ioapic.node = NUMA_NO_NODE; in ioapic_copy_alloc_attr()
827 dst->ioapic.is_level = level; in ioapic_copy_alloc_attr()
828 dst->ioapic.active_low = pol_low; in ioapic_copy_alloc_attr()
834 dst->ioapic.is_level = true; in ioapic_copy_alloc_attr()
835 dst->ioapic.active_low = true; in ioapic_copy_alloc_attr()
842 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE; in ioapic_alloc_attr_node()
868 * and polarity attributes. So allow the first user to reprogram the in mp_check_pin_attr()
869 * pin with real trigger and polarity attributes. in mp_check_pin_attr()
871 if (irq < nr_legacy_irqs() && data->count == 1) { in mp_check_pin_attr()
872 if (info->ioapic.is_level != data->is_level) in mp_check_pin_attr()
873 mp_register_handler(irq, info->ioapic.is_level); in mp_check_pin_attr()
874 data->entry.is_level = data->is_level = info->ioapic.is_level; in mp_check_pin_attr()
875 data->entry.active_low = data->active_low = info->ioapic.active_low; in mp_check_pin_attr()
878 return data->is_level == info->ioapic.is_level && in mp_check_pin_attr()
879 data->active_low == info->ioapic.active_low; in mp_check_pin_attr()
887 int irq = -1; in alloc_irq_from_domain()
892 * Dynamically allocate IRQ number for non-ISA IRQs in the first in alloc_irq_from_domain()
906 return -1; in alloc_irq_from_domain()
916 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
917 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
918 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
923 static int alloc_isa_irq_from_domain(struct irq_domain *domain, int irq, int ioapic, int pin, in alloc_isa_irq_from_domain() argument
931 * Legacy ISA IRQ has already been allocated, just add pin to in alloc_isa_irq_from_domain()
932 * the pin list associated with this IRQ and program the IOAPIC in alloc_isa_irq_from_domain()
935 if (irq_data && irq_data->parent_data) { in alloc_isa_irq_from_domain()
937 return -EBUSY; in alloc_isa_irq_from_domain()
938 if (!add_pin_to_irq_node(irq_data->chip_data, node, ioapic, info->ioapic.pin)) in alloc_isa_irq_from_domain()
939 return -ENOMEM; in alloc_isa_irq_from_domain()
941 info->flags |= X86_IRQ_ALLOC_LEGACY; in alloc_isa_irq_from_domain()
945 data = irq_data->chip_data; in alloc_isa_irq_from_domain()
946 data->isa_irq = true; in alloc_isa_irq_from_domain()
953 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, in mp_map_pin_to_irq() argument
963 return -ENOSYS; in mp_map_pin_to_irq()
977 return -EINVAL; in mp_map_pin_to_irq()
983 irq = irq_find_mapping(domain, pin); in mp_map_pin_to_irq()
985 irq = -ENOENT; in mp_map_pin_to_irq()
988 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); in mp_map_pin_to_irq()
991 ioapic, pin, &tmp); in mp_map_pin_to_irq()
992 else if ((irq = irq_find_mapping(domain, pin)) == 0) in mp_map_pin_to_irq()
995 irq = -EBUSY; in mp_map_pin_to_irq()
998 data->count++; in mp_map_pin_to_irq()
1004 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) in pin_2_irq() argument
1006 u32 gsi = mp_pin_to_gsi(ioapic, pin); in pin_2_irq()
1009 if (mp_irqs[idx].dstirq != pin) in pin_2_irq()
1014 if ((pin >= 16) && (pin <= 23)) { in pin_2_irq()
1015 if (pirq_entries[pin - 16] != -1) { in pin_2_irq()
1016 if (!pirq_entries[pin - 16]) { in pin_2_irq()
1017 apic_pr_verbose("Disabling PIRQ%d\n", pin - 16); in pin_2_irq()
1019 int irq = pirq_entries[pin-16]; in pin_2_irq()
1021 apic_pr_verbose("Using PIRQ%d -> IRQ %d\n", pin - 16, irq); in pin_2_irq()
1028 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); in pin_2_irq()
1033 int ioapic, pin, idx; in mp_map_gsi_to_irq() local
1037 return -ENODEV; in mp_map_gsi_to_irq()
1039 pin = mp_find_ioapic_pin(ioapic, gsi); in mp_map_gsi_to_irq()
1040 idx = find_irq_entry(ioapic, pin, mp_INT); in mp_map_gsi_to_irq()
1042 return -ENODEV; in mp_map_gsi_to_irq()
1044 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); in mp_map_gsi_to_irq()
1052 if (!irq_data || !irq_data->domain) in mp_unmap_irq()
1055 data = irq_data->chip_data; in mp_unmap_irq()
1056 if (!data || data->isa_irq) in mp_unmap_irq()
1060 if (--data->count == 0) in mp_unmap_irq()
1068 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) in IO_APIC_get_PCI_irq_vector() argument
1070 int irq, i, best_ioapic = -1, best_idx = -1; in IO_APIC_get_PCI_irq_vector()
1072 apic_pr_debug("Querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", in IO_APIC_get_PCI_irq_vector()
1073 bus, slot, pin); in IO_APIC_get_PCI_irq_vector()
1076 return -1; in IO_APIC_get_PCI_irq_vector()
1101 if (pin == (mp_irqs[i].srcbusirq & 3)) { in IO_APIC_get_PCI_irq_vector()
1108 * Use the first all-but-pin matching entry as a in IO_APIC_get_PCI_irq_vector()
1109 * best-guess fuzzy result for broken mptables. in IO_APIC_get_PCI_irq_vector()
1117 return -1; in IO_APIC_get_PCI_irq_vector()
1128 unsigned int ioapic, pin; in setup_IO_APIC_irqs() local
1133 for_each_ioapic_pin(ioapic, pin) { in setup_IO_APIC_irqs()
1134 idx = find_irq_entry(ioapic, pin, mp_INT); in setup_IO_APIC_irqs()
1136 apic_pr_verbose("apic %d pin %d not connected\n", in setup_IO_APIC_irqs()
1137 mpc_ioapic_id(ioapic), pin); in setup_IO_APIC_irqs()
1139 pin_2_irq(idx, ioapic, pin, ioapic ? 0 : IOAPIC_MAP_ALLOC); in setup_IO_APIC_irqs()
1158 snprintf(buf, sizeof(buf), " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", in io_apic_print_entries()
1232 apic_dbg("number of IO-APIC #%d registers: %d.\n", in print_IO_APICs()
1245 apic_dbg("IRQ to pin mappings:\n"); in print_IO_APICs()
1257 if (list_empty(&data->irq_2_pin)) in print_IO_APICs()
1261 for_each_irq_pin(entry, data->irq_2_pin) in print_IO_APICs()
1262 pr_cont("-> %d:%d", entry->apic, entry->pin); in print_IO_APICs()
1270 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; member
1274 int i8259_apic, i8259_pin, apic, pin; in enable_IO_APIC() local
1282 for_each_ioapic_pin(apic, pin) { in enable_IO_APIC()
1284 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); in enable_IO_APIC()
1288 * have found the pin where the i8259 is connected. in enable_IO_APIC()
1292 ioapic_i8259.pin = pin; in enable_IO_APIC()
1300 * If we could not find the appropriate pin by looking at the ioapic in enable_IO_APIC()
1307 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { in enable_IO_APIC()
1309 ioapic_i8259.pin = i8259_pin; in enable_IO_APIC()
1313 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && in enable_IO_APIC()
1314 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) in enable_IO_APIC()
1317 /* Do not trust the IO-APIC being empty at bootup */ in enable_IO_APIC()
1327 if (ioapic_i8259.pin != -1) { in native_restore_boot_irq_mode()
1340 /* Add it to the IO-APIC irq-routing table */ in native_restore_boot_irq_mode()
1341 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); in native_restore_boot_irq_mode()
1345 disconnect_bsp_APIC(ioapic_i8259.pin != -1); in native_restore_boot_irq_mode()
1358 * function to set the IO-APIC physical IDs based on the
1388 pr_err(FW_BUG "IO-APIC#%d ID is %d in the MPC table!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1397 * 'stuck on smp_invalidate_needed IPI wait' messages. in setup_ioapic_ids_from_mpc_nocheck()
1400 pr_err(FW_BUG "IO-APIC#%d ID %d is already used!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1434 apic_pr_verbose("...changing IO-APIC physical APIC ID to %d ...", in setup_ioapic_ids_from_mpc_nocheck()
1491 } while ((now - start) < 40000000000ULL / HZ && time_before_eq(jiffies, end)); in delay_with_tsc()
1515 * - timer IRQ defaults to IO-APIC IRQ
1516 * - if this function detects that timer IRQs are defunct, then we fall
1535 * ticks in a non-ExtINT mode. Also the local APIC in timer_irq_works()
1557 * Starting up a edge-triggered IO-APIC interrupt is nasty - we need to
1561 * This is not complete - we should be able to fake an edge even if it
1566 int was_pending = 0, irq = data->irq; in startup_ioapic_irq()
1570 legacy_pic->mask(irq); in startup_ioapic_irq()
1571 if (legacy_pic->irq_pending(irq)) in startup_ioapic_irq()
1574 __unmask_ioapic(data->chip_data); in startup_ioapic_irq()
1586 for_each_irq_pin(entry, data->irq_2_pin) { in io_apic_level_ack_pending()
1588 int pin; in io_apic_level_ack_pending() local
1590 pin = entry->pin; in io_apic_level_ack_pending()
1591 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2); in io_apic_level_ack_pending()
1623 * - On any sane system the read of the ioapic will in ioapic_finish_move()
1626 * - We get to see if the ACK has actually been delivered. in ioapic_finish_move()
1640 if (!io_apic_level_ack_pending(data->chip_data)) in ioapic_finish_move()
1670 * chipsets). Under certain conditions a level-triggered interrupt is in ioapic_ack_level()
1671 * erroneously delivered as edge-triggered one but the respective IRR in ioapic_ack_level()
1682 * level-triggered interrupt. We mask the source for the time of the in ioapic_ack_level()
1683 * operation to prevent an edge-triggered interrupt escaping meanwhile. in ioapic_ack_level()
1684 * The idea is from Manfred Spraul. --macro in ioapic_ack_level()
1690 * level-triggered io-apic interrupt will be seen as an edge in ioapic_ack_level()
1692 * to be broadcasted to the IO-APIC's which will clear the remoteIRR in ioapic_ack_level()
1693 * corresponding to the level-triggered interrupt. Hence on IO-APIC's in ioapic_ack_level()
1695 * remote IRR and on IO-APIC's which don't have an EOI register, in ioapic_ack_level()
1699 i = cfg->vector; in ioapic_ack_level()
1710 * message via io-apic EOI register write or simulating it using in ioapic_ack_level()
1717 eoi_ioapic_pin(cfg->vector, irq_data->chip_data); in ioapic_ack_level()
1725 struct mp_chip_data *data = irq_data->chip_data; in ioapic_ir_ack_level()
1728 * Intr-remapping uses pin number as the virtual vector in ioapic_ir_ack_level()
1730 * intr-remapping table entry. Hence for the io-apic in ioapic_ir_ack_level()
1731 * EOI we use the pin number. in ioapic_ir_ack_level()
1734 eoi_ioapic_pin(data->entry.vector, data); in ioapic_ir_ack_level()
1762 * - Real vector in ioapic_setup_msg_from_msi()
1763 * - DMAR/IR: 8bit subhandle (ioapic.pin) in ioapic_setup_msg_from_msi()
1764 * - AMD/IR: 8bit IRTE index in ioapic_setup_msg_from_msi()
1766 entry->vector = msg.arch_data.vector; in ioapic_setup_msg_from_msi()
1768 entry->delivery_mode = msg.arch_data.delivery_mode; in ioapic_setup_msg_from_msi()
1770 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical; in ioapic_setup_msg_from_msi()
1772 entry->ir_format = msg.arch_addr_lo.dmar_format; in ioapic_setup_msg_from_msi()
1774 * - DMAR/IR: index bit 0-14. in ioapic_setup_msg_from_msi()
1776 * - Virt: If the host supports x2apic without a virtualized IR in ioapic_setup_msg_from_msi()
1777 * unit then bit 0-6 of dmar_index_0_14 are providing bit in ioapic_setup_msg_from_msi()
1778 * 8-14 of the destination id. in ioapic_setup_msg_from_msi()
1780 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the in ioapic_setup_msg_from_msi()
1781 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7). in ioapic_setup_msg_from_msi()
1783 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14; in ioapic_setup_msg_from_msi()
1788 struct mp_chip_data *mpd = irqd->chip_data; in ioapic_configure_entry()
1791 ioapic_setup_msg_from_msi(irqd, &mpd->entry); in ioapic_configure_entry()
1793 for_each_irq_pin(entry, mpd->irq_2_pin) in ioapic_configure_entry()
1794 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); in ioapic_configure_entry()
1799 struct irq_data *parent = irq_data->parent_data; in ioapic_set_affinity()
1802 ret = parent->chip->irq_set_affinity(parent, mask, force); in ioapic_set_affinity()
1812 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1823 * Verify that the corresponding Remote-IRR bits are clear.
1828 struct mp_chip_data *mcd = irqd->chip_data; in ioapic_irq_get_chip_state()
1833 return -EINVAL; in ioapic_irq_get_chip_state()
1838 for_each_irq_pin(p, mcd->irq_2_pin) { in ioapic_irq_get_chip_state()
1839 rentry = __ioapic_read_entry(p->apic, p->pin); in ioapic_irq_get_chip_state()
1843 * irrelevant because the IO-APIC treats them as fire and in ioapic_irq_get_chip_state()
1855 .name = "IO-APIC",
1869 .name = "IR-IO-APIC",
1889 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { in init_IO_APIC_traps()
1892 * default to an old-fashioned 8259 interrupt if we in init_IO_APIC_traps()
1896 legacy_pic->make_irq(irq); in init_IO_APIC_traps()
1904 * The local APIC irq-chip implementation:
1926 .name = "local-APIC",
1942 * cycles as some i82489DX-based boards have glue logic that keeps the
1943 * 8259A interrupt line asserted until INTA. --macro
1949 int apic, pin, i; in unlock_ExtINT_logic() local
1952 pin = find_isa_irq_pin(8, mp_INT); in unlock_ExtINT_logic()
1953 if (pin == -1) { in unlock_ExtINT_logic()
1958 if (apic == -1) { in unlock_ExtINT_logic()
1963 entry0 = ioapic_read_entry(apic, pin); in unlock_ExtINT_logic()
1964 clear_IO_APIC_pin(apic, pin); in unlock_ExtINT_logic()
1978 ioapic_write_entry(apic, pin, entry1); in unlock_ExtINT_logic()
1987 while (i-- > 0) { in unlock_ExtINT_logic()
1990 i -= 10; in unlock_ExtINT_logic()
1995 clear_IO_APIC_pin(apic, pin); in unlock_ExtINT_logic()
1997 ioapic_write_entry(apic, pin, entry0); in unlock_ExtINT_logic()
2001 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2009 static int __init mp_alloc_timer_irq(int ioapic, int pin) in mp_alloc_timer_irq() argument
2012 int irq = -1; in mp_alloc_timer_irq()
2019 info.ioapic.pin = pin; in mp_alloc_timer_irq()
2021 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); in mp_alloc_timer_irq()
2033 for_each_irq_pin(entry, data->irq_2_pin) { in replace_pin_at_irq_node()
2034 if (entry->apic == oldapic && entry->pin == oldpin) { in replace_pin_at_irq_node()
2035 entry->apic = newapic; in replace_pin_at_irq_node()
2036 entry->pin = newpin; in replace_pin_at_irq_node()
2041 /* Old apic/pin didn't exist, so just add a new one */ in replace_pin_at_irq_node()
2054 struct mp_chip_data *data = irq_data->chip_data; in check_timer()
2068 legacy_pic->mask(0); in check_timer()
2075 * watchdog as that APIC treats NMIs as level-triggered. in check_timer()
2080 legacy_pic->init(1); in check_timer()
2084 pin2 = ioapic_i8259.pin; in check_timer()
2088 cfg->vector, apic1, pin1, apic2, pin2); in check_timer()
2093 * interrupt input. So just in case, if only one pin in check_timer()
2097 if (pin1 == -1) { in check_timer()
2098 panic_if_irq_remap(FW_BUG "Timer not connected to IO-APIC"); in check_timer()
2102 } else if (pin2 == -1) { in check_timer()
2107 if (pin1 != -1) { in check_timer()
2114 * so only need to unmask if it is level-trigger in check_timer()
2119 if (idx != -1 && irq_is_level(idx)) in check_timer()
2129 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); in check_timer()
2132 pr_err("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n"); in check_timer()
2135 pr_info("..... (found apic %d pin %d) ...\n", apic2, pin2); in check_timer()
2142 legacy_pic->unmask(0); in check_timer()
2150 legacy_pic->mask(0); in check_timer()
2158 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ in check_timer()
2159 legacy_pic->unmask(0); in check_timer()
2165 legacy_pic->mask(0); in check_timer()
2166 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); in check_timer()
2171 legacy_pic->init(0); in check_timer()
2172 legacy_pic->make_irq(0); in check_timer()
2174 legacy_pic->unmask(0); in check_timer()
2185 pr_info("Perhaps problem with the pre-enabled x2apic mode\n" in check_timer()
2186 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); in check_timer()
2188 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " in check_timer()
2196 * to devices. However there may be an I/O APIC pin available for
2197 * this interrupt regardless. The pin may be left unconnected, but
2199 * the master 8259A. In the MPS case such a pin will normally be
2203 * interrupt, that is edge-triggered and unmasked by default. We
2209 * it anyway. --macro
2218 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; in mp_irqdomain_create()
2223 if (cfg->type == IOAPIC_DOMAIN_INVALID) in mp_irqdomain_create()
2227 if (cfg->dev) { in mp_irqdomain_create()
2228 fn = of_fwnode_handle(cfg->dev); in mp_irqdomain_create()
2230 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic)); in mp_irqdomain_create()
2232 return -ENOMEM; in mp_irqdomain_create()
2241 if (!cfg->dev) in mp_irqdomain_create()
2243 return -ENODEV; in mp_irqdomain_create()
2246 ip->irqdomain = irq_domain_create_hierarchy(parent, 0, hwirqs, fn, cfg->ops, in mp_irqdomain_create()
2248 if (!ip->irqdomain) { in mp_irqdomain_create()
2250 if (!cfg->dev) in mp_irqdomain_create()
2252 return -ENOMEM; in mp_irqdomain_create()
2255 if (cfg->type == IOAPIC_DOMAIN_LEGACY || cfg->type == IOAPIC_DOMAIN_STRICT) in mp_irqdomain_create()
2256 ioapic_dynirq_base = max(ioapic_dynirq_base, gsi_cfg->gsi_end + 1); in mp_irqdomain_create()
2264 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode; in ioapic_destroy_irqdomain()
2268 if (!cfg->dev) in ioapic_destroy_irqdomain()
2283 apic_pr_verbose("ENABLING IO-APIC IRQs\n"); in setup_IO_APIC()
2287 /* Set up IO-APIC IRQ routing. */ in setup_IO_APIC()
2416 return -1; in io_apic_get_unique_id()
2529 * Ensure fixmaps for IO-APIC MMIO respect memory encryption pgprot in io_apic_set_fixmap()
2554 pr_err("WARNING: bogus zero IO-APIC address found in MPTABLE, " in io_apic_init_mappings()
2574 ioapic_res->start = ioapic_phys; in io_apic_init_mappings()
2575 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; in io_apic_init_mappings()
2602 return -1; in mp_find_ioapic()
2608 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) in mp_find_ioapic()
2613 return -1; in mp_find_ioapic()
2621 return -1; in mp_find_ioapic_pin()
2624 if (WARN_ON(gsi > gsi_cfg->gsi_end)) in mp_find_ioapic_pin()
2625 return -1; in mp_find_ioapic_pin()
2627 return gsi - gsi_cfg->gsi_base; in mp_find_ioapic_pin()
2640 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { in bad_ioapic_register()
2659 * mp_register_ioapic - Register an IOAPIC device
2674 return -EINVAL; in mp_register_ioapic()
2680 return -EEXIST; in mp_register_ioapic()
2688 return -ENOSPC; in mp_register_ioapic()
2698 return -ENODEV; in mp_register_ioapic()
2705 * Build basic GSI lookup table to facilitate gsi->io_apic lookups in mp_register_ioapic()
2709 gsi_end = gsi_base + entries - 1; in mp_register_ioapic()
2712 if ((gsi_base >= gsi_cfg->gsi_base && in mp_register_ioapic()
2713 gsi_base <= gsi_cfg->gsi_end) || in mp_register_ioapic()
2714 (gsi_end >= gsi_cfg->gsi_base && in mp_register_ioapic()
2715 gsi_end <= gsi_cfg->gsi_end)) { in mp_register_ioapic()
2716 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", in mp_register_ioapic()
2717 gsi_base, gsi_end, gsi_cfg->gsi_base, gsi_cfg->gsi_end); in mp_register_ioapic()
2719 return -ENOSPC; in mp_register_ioapic()
2723 gsi_cfg->gsi_base = gsi_base; in mp_register_ioapic()
2724 gsi_cfg->gsi_end = gsi_end; in mp_register_ioapic()
2737 return -ENOMEM; in mp_register_ioapic()
2742 if (gsi_cfg->gsi_end >= gsi_top) in mp_register_ioapic()
2743 gsi_top = gsi_cfg->gsi_end + 1; in mp_register_ioapic()
2750 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", in mp_register_ioapic()
2752 gsi_cfg->gsi_base, gsi_cfg->gsi_end); in mp_register_ioapic()
2759 int ioapic, pin; in mp_unregister_ioapic() local
2771 return -ENODEV; in mp_unregister_ioapic()
2774 for_each_pin(ioapic, pin) { in mp_unregister_ioapic()
2775 u32 gsi = mp_pin_to_gsi(ioapic, pin); in mp_unregister_ioapic()
2781 if (data && data->count) { in mp_unregister_ioapic()
2782 pr_warn("pin%d on IOAPIC%d is still in use.\n", pin, ioapic); in mp_unregister_ioapic()
2783 return -EBUSY; in mp_unregister_ioapic()
2814 if (info && info->ioapic.valid) { in mp_irqdomain_get_attr()
2815 data->is_level = info->ioapic.is_level; in mp_irqdomain_get_attr()
2816 data->active_low = info->ioapic.active_low; in mp_irqdomain_get_attr()
2817 } else if (__acpi_get_override_irq(gsi, &data->is_level, &data->active_low) < 0) { in mp_irqdomain_get_attr()
2819 data->is_level = true; in mp_irqdomain_get_attr()
2820 data->active_low = true; in mp_irqdomain_get_attr()
2825 * Configure the I/O-APIC specific fields in the routing entry.
2827 * This is important to setup the I/O-APIC specific bits (is_level,
2829 * provide the routing information and is oblivious of the I/O-APIC
2838 struct IO_APIC_route_entry *entry = &data->entry; in mp_preconfigure_entry()
2841 entry->is_level = data->is_level; in mp_preconfigure_entry()
2842 entry->active_low = data->active_low; in mp_preconfigure_entry()
2847 entry->masked = data->is_level; in mp_preconfigure_entry()
2856 int ret, ioapic, pin; in mp_irqdomain_alloc() local
2860 return -EINVAL; in mp_irqdomain_alloc()
2863 return -EINVAL; in mp_irqdomain_alloc()
2866 pin = info->ioapic.pin; in mp_irqdomain_alloc()
2867 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) in mp_irqdomain_alloc()
2868 return -EEXIST; in mp_irqdomain_alloc()
2872 return -ENOMEM; in mp_irqdomain_alloc()
2878 INIT_LIST_HEAD(&data->irq_2_pin); in mp_irqdomain_alloc()
2879 irq_data->hwirq = info->ioapic.pin; in mp_irqdomain_alloc()
2880 irq_data->chip = (domain->parent == x86_vector_domain) ? in mp_irqdomain_alloc()
2882 irq_data->chip_data = data; in mp_irqdomain_alloc()
2883 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); in mp_irqdomain_alloc()
2885 if (!add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin)) { in mp_irqdomain_alloc()
2886 ret = -ENOMEM; in mp_irqdomain_alloc()
2891 mp_register_handler(virq, data->is_level); in mp_irqdomain_alloc()
2895 legacy_pic->mask(virq); in mp_irqdomain_alloc()
2898 …apic_pr_verbose("IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n… in mp_irqdomain_alloc()
2899 ioapic, mpc_ioapic_id(ioapic), pin, virq, data->is_level, data->active_low); in mp_irqdomain_alloc()
2917 if (irq_data && irq_data->chip_data) { in mp_irqdomain_free()
2918 data = irq_data->chip_data; in mp_irqdomain_free()
2919 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq); in mp_irqdomain_free()
2920 WARN_ON(!list_empty(&data->irq_2_pin)); in mp_irqdomain_free()
2921 kfree(irq_data->chip_data); in mp_irqdomain_free()
2937 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq); in mp_irqdomain_deactivate()
2942 return (int)(long)domain->host_data; in mp_irqdomain_ioapic_idx()