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Searched +full:ufshcd +full:- +full:pltfrm (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/ufs/host/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o
4 obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o
5 obj-$(CONFIG_SCSI_UFS_CDNS_PLATFORM) += cdns-pltfrm.o
6 obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
7 obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o
8 obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
9 obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
10 obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
11 obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
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H A Dtc-dwc-g210-pltfrm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
17 #include "ufshcd-pltfrm.h"
18 #include "ufshcd-dwc.h"
19 #include "tc-dwc-g210.h"
25 .name = "tc-dwc-g210-pltfm",
31 .name = "tc-dwc-g210-pltfm",
38 .compatible = "snps,g210-tc-6.00-20bit",
42 .compatible = "snps,g210-tc-6.00-40bit",
59 struct device *dev = &pdev->dev; in tc_dwc_g210_pltfm_probe()
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H A Dcdns-pltfrm.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "ufshcd-pltfrm.h"
27 * cdns_ufs_dme_attr_val - for storing L4 attributes
33 * cdns_ufs_get_l4_attr - get L4 attributes on local side
42 &host->cdns_ufs_dme_attr_val[0]); in cdns_ufs_get_l4_attr()
44 &host->cdns_ufs_dme_attr_val[1]); in cdns_ufs_get_l4_attr()
46 &host->cdns_ufs_dme_attr_val[2]); in cdns_ufs_get_l4_attr()
48 &host->cdns_ufs_dme_attr_val[3]); in cdns_ufs_get_l4_attr()
50 &host->cdns_ufs_dme_attr_val[4]); in cdns_ufs_get_l4_attr()
52 &host->cdns_ufs_dme_attr_val[5]); in cdns_ufs_get_l4_attr()
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H A Dufs-sprd.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/arm-smccc.h>
17 #include <ufs/ufshcd.h>
18 #include "ufshcd-pltfrm.h"
19 #include "ufs-sprd.h"
27 WARN_ON(!host->priv); in ufs_sprd_get_priv_data()
28 return host->priv; in ufs_sprd_get_priv_data()
34 regmap_update_bits(priv->sysci[index].regmap, reg, bits, val); in ufs_sprd_regmap_update()
40 regmap_read(priv->sysci[index].regmap, reg, val); in ufs_sprd_regmap_read()
47 if (ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &host->unipro_ver)) in ufs_sprd_get_unipro_ver()
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H A Dufs-renesas.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
17 #include <ufs/ufshcd.h>
19 #include "ufshcd-pltfrm.h"
287 WARN_ON(p->index >= MAX_INDEX); in ufs_renesas_reg_control()
289 switch (p->mode) { in ufs_renesas_reg_control()
291 ufshcd_writel(hba, save[p->index], p->reg); in ufs_renesas_reg_control()
294 save[p->index] |= p->u.set; in ufs_renesas_reg_control()
297 save[p->index] = ufshcd_readl(hba, p->reg) & p->mask; in ufs_renesas_reg_control()
300 ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg, in ufs_renesas_reg_control()
302 (val & p->mask) == p->u.expected, in ufs_renesas_reg_control()
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H A Dufs-hisi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2016-2017 Linaro Ltd.
6 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
14 #include <linux/dma-mapping.h>
18 #include <ufs/ufshcd.h>
19 #include "ufshcd-pltfrm.h"
21 #include "ufs-hisi.h"
57 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_hisi_check_hibern8()
61 err = -1; in ufs_hisi_check_hibern8()
62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
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H A Dufshcd-pltfrm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011-2013 Samsung India Software Operations
18 #include <ufs/ufshcd.h>
19 #include "ufshcd-pltfrm.h"
29 struct device *dev = hba->dev; in ufshcd_parse_clock_info()
30 struct device_node *np = dev->of_node; in ufshcd_parse_clock_info()
39 cnt = of_property_count_strings(np, "clock-names"); in ufshcd_parse_clock_info()
40 if (!cnt || (cnt == -EINVAL)) { in ufshcd_parse_clock_info()
52 sz = of_property_count_u32_elems(np, "freq-table-hz"); in ufshcd_parse_clock_info()
54 dev_info(dev, "freq-table-hz property not specified\n"); in ufshcd_parse_clock_info()
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H A Dufs-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/arm-smccc.h>
23 #include <ufs/ufshcd.h>
24 #include "ufshcd-pltfrm.h"
28 #include "ufs-mediatek.h"
29 #include "ufs-mediatek-sip.h"
34 #include "ufs-mediatek-trace.h"
52 { .compatible = "mediatek,mt8183-ufshci" },
99 return !!(host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE); in ufs_mtk_is_boost_crypt_enabled()
106 return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL); in ufs_mtk_is_va09_supported()
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H A Dufs-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
21 #include <ufs/ufshcd.h>
25 #include "ufshcd-pltfrm.h"
26 #include "ufs-qcom.h"
111 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
112 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
117 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init()
118 struct device *dev = hba->dev; in ufs_qcom_ice_init()
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H A Dufs-exynos.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
13 #include <linux/arm-smccc.h>
24 #include <ufs/ufshcd.h>
25 #include "ufshcd-pltfrm.h"
29 #include "ufs-exynos.h"
95 /* Multi-host registers */
208 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynosauto_ufs_drv_init()
211 if (ufs->sysreg) { in exynosauto_ufs_drv_init()
212 return regmap_update_bits(ufs->sysreg, in exynosauto_ufs_drv_init()
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