Lines Matching +full:ufshcd +full:- +full:pltfrm
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
13 #include <linux/arm-smccc.h>
24 #include <ufs/ufshcd.h>
25 #include "ufshcd-pltfrm.h"
29 #include "ufs-exynos.h"
95 /* Multi-host registers */
208 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynosauto_ufs_drv_init()
211 if (ufs->sysreg) { in exynosauto_ufs_drv_init()
212 return regmap_update_bits(ufs->sysreg, in exynosauto_ufs_drv_init()
213 ufs->shareability_reg_offset, in exynosauto_ufs_drv_init()
217 attr->tx_dif_p_nsec = 3200000; in exynosauto_ufs_drv_init()
224 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_hce_enable()
238 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link()
242 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
243 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
248 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
265 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
293 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change()
306 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change()
319 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos7_ufs_pre_link()
320 u32 val = attr->pa_dbg_opt_suite1_val; in exynos7_ufs_pre_link()
321 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link()
338 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in exynos7_ufs_pre_link()
344 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); in exynos7_ufs_pre_link()
351 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link()
381 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change()
382 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx); in exynos7_ufs_post_pwr_change()
396 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
398 * - Before host controller S/W reset
399 * - Access to UFS protector's register
427 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info()
428 struct list_head *head = &hba->clk_list_head; in exynos_ufs_get_clk_info()
439 if (!IS_ERR(clki->clk)) { in exynos_ufs_get_clk_info()
440 if (!strcmp(clki->name, "core_clk")) in exynos_ufs_get_clk_info()
441 ufs->clk_hci_core = clki->clk; in exynos_ufs_get_clk_info()
442 else if (!strcmp(clki->name, "sclk_unipro_main")) in exynos_ufs_get_clk_info()
443 ufs->clk_unipro_main = clki->clk; in exynos_ufs_get_clk_info()
447 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { in exynos_ufs_get_clk_info()
448 dev_err(hba->dev, "failed to get clk info\n"); in exynos_ufs_get_clk_info()
449 ret = -EINVAL; in exynos_ufs_get_clk_info()
453 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); in exynos_ufs_get_clk_info()
454 pclk_rate = clk_get_rate(ufs->clk_hci_core); in exynos_ufs_get_clk_info()
455 f_min = ufs->pclk_avail_min; in exynos_ufs_get_clk_info()
456 f_max = ufs->pclk_avail_max; in exynos_ufs_get_clk_info()
458 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_get_clk_info()
469 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
470 ret = -EINVAL; in exynos_ufs_get_clk_info()
474 ufs->pclk_rate = pclk_rate; in exynos_ufs_get_clk_info()
475 ufs->pclk_div = div; in exynos_ufs_get_clk_info()
483 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_set_unipro_pclk_div()
487 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), in exynos_ufs_set_unipro_pclk_div()
494 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div()
495 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_set_pwm_clk_div()
498 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl); in exynos_ufs_set_pwm_clk_div()
503 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div()
504 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_calc_pwm_clk_div()
510 int i = 0, clk_idx = -1; in exynos_ufs_calc_pwm_clk_div()
523 if (clk_idx == -1) { in exynos_ufs_calc_pwm_clk_div()
525 dev_err(hba->dev, in exynos_ufs_calc_pwm_clk_div()
529 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK; in exynos_ufs_calc_pwm_clk_div()
535 long pclk_rate = ufs->pclk_rate; in exynos_ufs_calc_time_cntr()
546 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_specify_phy_time_attr()
547 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_specify_phy_time_attr()
549 t_cfg->tx_linereset_p = in exynos_ufs_specify_phy_time_attr()
550 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
551 t_cfg->tx_linereset_n = in exynos_ufs_specify_phy_time_attr()
552 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); in exynos_ufs_specify_phy_time_attr()
553 t_cfg->tx_high_z_cnt = in exynos_ufs_specify_phy_time_attr()
554 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); in exynos_ufs_specify_phy_time_attr()
555 t_cfg->tx_base_n_val = in exynos_ufs_specify_phy_time_attr()
556 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
557 t_cfg->tx_gran_n_val = in exynos_ufs_specify_phy_time_attr()
558 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
559 t_cfg->tx_sleep_cnt = in exynos_ufs_specify_phy_time_attr()
560 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
562 t_cfg->rx_linereset = in exynos_ufs_specify_phy_time_attr()
563 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
564 t_cfg->rx_hibern8_wait = in exynos_ufs_specify_phy_time_attr()
565 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); in exynos_ufs_specify_phy_time_attr()
566 t_cfg->rx_base_n_val = in exynos_ufs_specify_phy_time_attr()
567 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
568 t_cfg->rx_gran_n_val = in exynos_ufs_specify_phy_time_attr()
569 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
570 t_cfg->rx_sleep_cnt = in exynos_ufs_specify_phy_time_attr()
571 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
572 t_cfg->rx_stall_cnt = in exynos_ufs_specify_phy_time_attr()
573 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); in exynos_ufs_specify_phy_time_attr()
578 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr()
579 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_config_phy_time_attr()
588 ufs->drv_data->uic_attr->rx_filler_enable); in exynos_ufs_config_phy_time_attr()
590 RX_LINERESET(t_cfg->rx_linereset)); in exynos_ufs_config_phy_time_attr()
592 RX_BASE_NVAL_L(t_cfg->rx_base_n_val)); in exynos_ufs_config_phy_time_attr()
594 RX_BASE_NVAL_H(t_cfg->rx_base_n_val)); in exynos_ufs_config_phy_time_attr()
596 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
598 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
600 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt)); in exynos_ufs_config_phy_time_attr()
602 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt)); in exynos_ufs_config_phy_time_attr()
607 TX_LINERESET_P(t_cfg->tx_linereset_p)); in exynos_ufs_config_phy_time_attr()
609 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt)); in exynos_ufs_config_phy_time_attr()
611 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt)); in exynos_ufs_config_phy_time_attr()
613 TX_BASE_NVAL_L(t_cfg->tx_base_n_val)); in exynos_ufs_config_phy_time_attr()
615 TX_BASE_NVAL_H(t_cfg->tx_base_n_val)); in exynos_ufs_config_phy_time_attr()
617 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
619 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
622 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt)); in exynos_ufs_config_phy_time_attr()
624 ufs->drv_data->uic_attr->tx_min_activatetime); in exynos_ufs_config_phy_time_attr()
632 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr()
633 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_phy_cap_attr()
641 attr->rx_hs_g1_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
644 attr->rx_hs_g2_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
647 attr->rx_hs_g3_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
650 attr->rx_hs_g1_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
653 attr->rx_hs_g2_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
656 attr->rx_hs_g3_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
659 if (attr->rx_adv_fine_gran_sup_en == 0) { in exynos_ufs_config_phy_cap_attr()
664 if (attr->rx_min_actv_time_cap) in exynos_ufs_config_phy_cap_attr()
668 attr->rx_min_actv_time_cap); in exynos_ufs_config_phy_cap_attr()
670 if (attr->rx_hibern8_time_cap) in exynos_ufs_config_phy_cap_attr()
673 attr->rx_hibern8_time_cap); in exynos_ufs_config_phy_cap_attr()
675 } else if (attr->rx_adv_fine_gran_sup_en == 1) { in exynos_ufs_config_phy_cap_attr()
677 if (attr->rx_adv_fine_gran_step) in exynos_ufs_config_phy_cap_attr()
681 attr->rx_adv_fine_gran_step)); in exynos_ufs_config_phy_cap_attr()
683 if (attr->rx_adv_min_actv_time_cap) in exynos_ufs_config_phy_cap_attr()
687 attr->rx_adv_min_actv_time_cap); in exynos_ufs_config_phy_cap_attr()
689 if (attr->rx_adv_hibern8_time_cap) in exynos_ufs_config_phy_cap_attr()
693 attr->rx_adv_hibern8_time_cap); in exynos_ufs_config_phy_cap_attr()
702 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt()
743 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask()
744 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx); in exynos_ufs_config_sync_pattern_mask()
779 struct phy *generic_phy = ufs->phy; in exynos_ufs_pre_pwr_mode()
785 ret = -EINVAL; in exynos_ufs_pre_pwr_mode()
797 if (ufs->drv_data->pre_pwr_change) in exynos_ufs_pre_pwr_mode()
798 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); in exynos_ufs_pre_pwr_mode()
803 switch (dev_req_params->hs_rate) { in exynos_ufs_pre_pwr_mode()
826 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_pwr_mode()
827 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx); in exynos_ufs_post_pwr_mode()
828 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx); in exynos_ufs_post_pwr_mode()
838 if (ufs->drv_data->post_pwr_change) in exynos_ufs_post_pwr_mode()
839 ufs->drv_data->post_pwr_change(ufs, pwr_req); in exynos_ufs_post_pwr_mode()
842 switch (pwr_req->hs_rate) { in exynos_ufs_post_pwr_mode()
850 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B", in exynos_ufs_post_pwr_mode()
857 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); in exynos_ufs_post_pwr_mode()
900 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init()
901 struct phy *generic_phy = ufs->phy; in exynos_ufs_phy_init()
904 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { in exynos_ufs_phy_init()
906 &ufs->avail_ln_rx); in exynos_ufs_phy_init()
908 &ufs->avail_ln_tx); in exynos_ufs_phy_init()
909 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, in exynos_ufs_phy_init()
911 ufs->avail_ln_rx, ufs->avail_ln_tx); in exynos_ufs_phy_init()
914 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); in exynos_ufs_phy_init()
917 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in exynos_ufs_phy_init()
936 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_unipro()
937 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro()
939 if (attr->pa_dbg_clk_period_off) in exynos_ufs_config_unipro()
940 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), in exynos_ufs_config_unipro()
941 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynos_ufs_config_unipro()
944 ufs->drv_data->uic_attr->tx_trailingclks); in exynos_ufs_config_unipro()
946 if (attr->pa_dbg_opt_suite1_off) in exynos_ufs_config_unipro()
947 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in exynos_ufs_config_unipro()
948 attr->pa_dbg_opt_suite1_val); in exynos_ufs_config_unipro()
950 if (attr->pa_dbg_opt_suite2_off) in exynos_ufs_config_unipro()
951 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), in exynos_ufs_config_unipro()
952 attr->pa_dbg_opt_suite2_val); in exynos_ufs_config_unipro()
985 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
990 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
1010 /* m-phy */ in exynos_ufs_pre_link()
1012 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { in exynos_ufs_pre_link()
1019 if (ufs->drv_data->pre_link) in exynos_ufs_pre_link()
1020 ufs->drv_data->pre_link(ufs); in exynos_ufs_pre_link()
1030 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { in exynos_ufs_fit_aggr_timeout()
1043 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_link()
1044 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_post_link()
1052 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1053 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1056 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) in exynos_ufs_post_link()
1060 if (attr->pa_granularity) { in exynos_ufs_post_link()
1063 attr->pa_granularity); in exynos_ufs_post_link()
1066 if (attr->pa_tactivate) in exynos_ufs_post_link()
1068 attr->pa_tactivate); in exynos_ufs_post_link()
1069 if (attr->pa_hibern8time && in exynos_ufs_post_link()
1070 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) in exynos_ufs_post_link()
1072 attr->pa_hibern8time); in exynos_ufs_post_link()
1075 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_post_link()
1076 if (!attr->pa_granularity) in exynos_ufs_post_link()
1078 &attr->pa_granularity); in exynos_ufs_post_link()
1079 if (!attr->pa_hibern8time) in exynos_ufs_post_link()
1081 &attr->pa_hibern8time); in exynos_ufs_post_link()
1087 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) { in exynos_ufs_post_link()
1089 dev_warn(hba->dev, in exynos_ufs_post_link()
1092 attr->pa_granularity); in exynos_ufs_post_link()
1093 attr->pa_granularity = 6; in exynos_ufs_post_link()
1099 if (ufs->drv_data->post_link) in exynos_ufs_post_link()
1100 ufs->drv_data->post_link(ufs); in exynos_ufs_post_link()
1107 struct device_node *np = dev->of_node; in exynos_ufs_parse_dt()
1111 ufs->drv_data = device_get_match_data(dev); in exynos_ufs_parse_dt()
1113 if (ufs->drv_data && ufs->drv_data->uic_attr) { in exynos_ufs_parse_dt()
1114 attr = ufs->drv_data->uic_attr; in exynos_ufs_parse_dt()
1117 ret = -EINVAL; in exynos_ufs_parse_dt()
1121 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); in exynos_ufs_parse_dt()
1122 if (IS_ERR(ufs->sysreg)) in exynos_ufs_parse_dt()
1123 ufs->sysreg = NULL; in exynos_ufs_parse_dt()
1126 &ufs->shareability_reg_offset)) { in exynos_ufs_parse_dt()
1128 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET; in exynos_ufs_parse_dt()
1132 ufs->pclk_avail_min = PCLK_AVAIL_MIN; in exynos_ufs_parse_dt()
1133 ufs->pclk_avail_max = PCLK_AVAIL_MAX; in exynos_ufs_parse_dt()
1135 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN; in exynos_ufs_parse_dt()
1136 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL; in exynos_ufs_parse_dt()
1137 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP; in exynos_ufs_parse_dt()
1138 attr->pa_granularity = PA_GRANULARITY_VAL; in exynos_ufs_parse_dt()
1139 attr->pa_tactivate = PA_TACTIVATE_VAL; in exynos_ufs_parse_dt()
1140 attr->pa_hibern8time = PA_HIBERN8TIME_VAL; in exynos_ufs_parse_dt()
1149 ufs->hba = hba; in exynos_ufs_priv_init()
1150 ufs->opts = ufs->drv_data->opts; in exynos_ufs_priv_init()
1151 ufs->rx_sel_idx = PA_MAXDATALANES; in exynos_ufs_priv_init()
1152 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) in exynos_ufs_priv_init()
1153 ufs->rx_sel_idx = 0; in exynos_ufs_priv_init()
1154 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1155 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1162 * hardware on Exynos and Exynos-based SoCs. The interface to this hardware is
1177 * struct fmp_sg_entry - nonstandard format of PRDT entries when FMP is enabled
1180 * bits of the 'size' field, i.e. the last 32-bit word. When these
1185 * @file_enckey: The first half of the AES-XTS key with all bytes reserved
1186 * @file_twkey: The second half of the AES-XTS key with all bytes reserved
1214 struct blk_crypto_profile *profile = &hba->crypto_profile; in exynos_ufs_fmp_init()
1231 * downstream driver source for gs101 and other Exynos-based SoCs. It in exynos_ufs_fmp_init()
1234 * on other Exynos-based SoCs too, and might even still be the only way in exynos_ufs_fmp_init()
1239 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) in exynos_ufs_fmp_init()
1250 dev_warn(hba->dev, in exynos_ufs_fmp_init()
1263 dev_err(hba->dev, in exynos_ufs_fmp_init()
1270 err = devm_blk_crypto_profile_init(hba->dev, profile, 0); in exynos_ufs_fmp_init()
1273 dev_err(hba->dev, "Failed to initialize crypto profile: %d\n", in exynos_ufs_fmp_init()
1277 profile->max_dun_bytes_supported = AES_BLOCK_SIZE; in exynos_ufs_fmp_init()
1278 profile->dev = hba->dev; in exynos_ufs_fmp_init()
1279 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] = in exynos_ufs_fmp_init()
1282 /* Advertise crypto support to ufshcd-core. */ in exynos_ufs_fmp_init()
1283 hba->caps |= UFSHCD_CAP_CRYPTO; in exynos_ufs_fmp_init()
1285 /* Advertise crypto quirks to ufshcd-core. */ in exynos_ufs_fmp_init()
1286 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE | in exynos_ufs_fmp_init()
1296 if (!(hba->caps & UFSHCD_CAP_CRYPTO)) in exynos_ufs_fmp_resume()
1302 dev_err(hba->dev, in exynos_ufs_fmp_resume()
1308 dev_err(hba->dev, in exynos_ufs_fmp_resume()
1315 key + AES_KEYSIZE_256 - (j + 1) * sizeof(u64))); in fmp_key_word()
1324 const u8 *enckey = crypt_ctx->bc_key->raw; in exynos_ufs_fmp_fill_prdt()
1326 u64 dun_lo = crypt_ctx->bc_dun[0]; in exynos_ufs_fmp_fill_prdt()
1327 u64 dun_hi = crypt_ctx->bc_dun[1]; in exynos_ufs_fmp_fill_prdt()
1331 if (WARN_ON_ONCE(!(hba->caps & UFSHCD_CAP_CRYPTO))) in exynos_ufs_fmp_fill_prdt()
1332 return -EIO; in exynos_ufs_fmp_fill_prdt()
1340 if (prd->base.size != cpu_to_le32(DATA_UNIT_SIZE - 1)) { in exynos_ufs_fmp_fill_prdt()
1341 dev_err(hba->dev, in exynos_ufs_fmp_fill_prdt()
1343 return -EIO; in exynos_ufs_fmp_fill_prdt()
1347 prd->base.size |= cpu_to_le32((FMP_ALGO_MODE_AES_XTS << 28) | in exynos_ufs_fmp_fill_prdt()
1351 prd->file_iv[0] = cpu_to_be64(dun_hi); in exynos_ufs_fmp_fill_prdt()
1352 prd->file_iv[1] = cpu_to_be64(dun_lo); in exynos_ufs_fmp_fill_prdt()
1356 prd->file_enckey[j] = fmp_key_word(enckey, j); in exynos_ufs_fmp_fill_prdt()
1357 prd->file_twkey[j] = fmp_key_word(twkey, j); in exynos_ufs_fmp_fill_prdt()
1384 struct device *dev = hba->dev; in exynos_ufs_init()
1391 return -ENOMEM; in exynos_ufs_init()
1393 /* exynos-specific hci */ in exynos_ufs_init()
1394 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynos_ufs_init()
1395 if (IS_ERR(ufs->reg_hci)) { in exynos_ufs_init()
1397 return PTR_ERR(ufs->reg_hci); in exynos_ufs_init()
1401 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); in exynos_ufs_init()
1402 if (IS_ERR(ufs->reg_unipro)) { in exynos_ufs_init()
1404 return PTR_ERR(ufs->reg_unipro); in exynos_ufs_init()
1408 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); in exynos_ufs_init()
1409 if (IS_ERR(ufs->reg_ufsp)) { in exynos_ufs_init()
1411 return PTR_ERR(ufs->reg_ufsp); in exynos_ufs_init()
1420 ufs->phy = devm_phy_get(dev, "ufs-phy"); in exynos_ufs_init()
1421 if (IS_ERR(ufs->phy)) { in exynos_ufs_init()
1422 ret = PTR_ERR(ufs->phy); in exynos_ufs_init()
1423 dev_err(dev, "failed to get ufs-phy\n"); in exynos_ufs_init()
1431 if (ufs->drv_data->drv_init) { in exynos_ufs_init()
1432 ret = ufs->drv_data->drv_init(dev, ufs); in exynos_ufs_init()
1434 dev_err(dev, "failed to init drv-data\n"); in exynos_ufs_init()
1443 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) in exynos_ufs_init()
1446 hba->host->dma_alignment = DATA_UNIT_SIZE - 1; in exynos_ufs_init()
1450 hba->priv = NULL; in exynos_ufs_init()
1470 dev_err(hba->dev, "timeout host sw-reset\n"); in exynos_ufs_host_reset()
1471 ret = -ETIMEDOUT; in exynos_ufs_host_reset()
1490 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_pre_hibern8()
1493 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_pre_hibern8()
1497 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_pre_hibern8()
1501 int h8_time = attr->pa_hibern8time * in exynos_ufs_pre_hibern8()
1502 granularity_tbl[attr->pa_granularity - 1]; in exynos_ufs_pre_hibern8()
1507 delta = h8_time - ktime_us_delta(ktime_get(), in exynos_ufs_pre_hibern8()
1508 ufs->entry_hibern8_t); in exynos_ufs_pre_hibern8()
1528 if (ufshcd_is_hs_mode(&ufs->dev_req_params)) in exynos_ufs_post_hibern8()
1535 dev_warn(hba->dev, "%s: power mode change\n", __func__); in exynos_ufs_post_hibern8()
1536 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; in exynos_ufs_post_hibern8()
1537 hba->pwr_info.pwr_tx = cur_mode & 0xf; in exynos_ufs_post_hibern8()
1538 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); in exynos_ufs_post_hibern8()
1541 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) in exynos_ufs_post_hibern8()
1544 ufs->entry_hibern8_t = ktime_get(); in exynos_ufs_post_hibern8()
1546 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_post_hibern8()
1565 hba->host->max_segment_size = DATA_UNIT_SIZE; in exynos_ufs_hce_enable_notify()
1567 if (ufs->drv_data->pre_hce_enable) { in exynos_ufs_hce_enable_notify()
1568 ret = ufs->drv_data->pre_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1580 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) in exynos_ufs_hce_enable_notify()
1583 if (ufs->drv_data->post_hce_enable) in exynos_ufs_hce_enable_notify()
1584 ret = ufs->drv_data->post_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1652 phy_power_off(ufs->phy); in exynos_ufs_suspend()
1662 phy_power_on(ufs->phy); in exynos_ufs_resume()
1699 return -ETIME; in exynosauto_ufs_vh_wait_ph_ready()
1704 struct device *dev = hba->dev; in exynosauto_ufs_vh_init()
1711 return -ENOMEM; in exynosauto_ufs_vh_init()
1713 /* exynos-specific hci */ in exynosauto_ufs_vh_init()
1714 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynosauto_ufs_vh_init()
1715 if (IS_ERR(ufs->reg_hci)) { in exynosauto_ufs_vh_init()
1717 return PTR_ERR(ufs->reg_hci); in exynosauto_ufs_vh_init()
1724 ufs->drv_data = device_get_match_data(dev); in exynosauto_ufs_vh_init()
1725 if (!ufs->drv_data) in exynosauto_ufs_vh_init()
1726 return -ENODEV; in exynosauto_ufs_vh_init()
1735 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in fsd_ufs_pre_link()
1736 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_link()
1739 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), in fsd_ufs_pre_link()
1740 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1746 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1752 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1764 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in fsd_ufs_pre_link()
1776 struct ufs_hba *hba = ufs->hba; in fsd_ufs_post_link()
1814 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_pwr_change()
1831 return (16 * 1000 * 1000000UL / ufs->mclk_rate); in get_mclk_period_unipro_18()
1836 struct ufs_hba *hba = ufs->hba; in gs101_ufs_pre_link()
1840 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) in gs101_ufs_pre_link()
1842 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) in gs101_ufs_pre_link()
1851 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in gs101_ufs_pre_link()
1866 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in gs101_ufs_pre_link()
1892 struct ufs_hba *hba = ufs->hba; in gs101_ufs_post_link()
1904 struct ufs_hba *hba = ufs->hba; in gs101_ufs_pre_pwr_change()
1943 struct device *dev = &pdev->dev; in exynos_ufs_probe()
1948 if (drv_data && drv_data->vops) in exynos_ufs_probe()
1949 vops = drv_data->vops; in exynos_ufs_probe()
1963 pm_runtime_get_sync(&(pdev)->dev); in exynos_ufs_remove()
1966 phy_power_off(ufs->phy); in exynos_ufs_remove()
1967 phy_exit(ufs->phy); in exynos_ufs_remove()
2136 { .compatible = "google,gs101-ufs",
2138 { .compatible = "samsung,exynos7-ufs",
2140 { .compatible = "samsung,exynosautov9-ufs",
2142 { .compatible = "samsung,exynosautov9-ufs-vh",
2144 { .compatible = "tesla,fsd-ufs",
2161 .name = "exynos-ufshc",