Lines Matching +full:ufshcd +full:- +full:pltfrm
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
21 #include <ufs/ufshcd.h>
25 #include "ufshcd-pltfrm.h"
26 #include "ufs-qcom.h"
111 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
112 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
117 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init()
118 struct device *dev = hba->dev; in ufs_qcom_ice_init()
122 if (ice == ERR_PTR(-EOPNOTSUPP)) { in ufs_qcom_ice_init()
130 host->ice = ice; in ufs_qcom_ice_init()
131 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_qcom_ice_init()
138 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_resume()
139 return qcom_ice_resume(host->ice); in ufs_qcom_ice_resume()
146 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_suspend()
147 return qcom_ice_suspend(host->ice); in ufs_qcom_ice_suspend()
159 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; in ufs_qcom_ice_program_key()
161 /* Only AES-256-XTS has been tested so far. */ in ufs_qcom_ice_program_key()
162 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; in ufs_qcom_ice_program_key()
165 return -EOPNOTSUPP; in ufs_qcom_ice_program_key()
168 return qcom_ice_program_key(host->ice, in ufs_qcom_ice_program_key()
171 cfg->crypto_key, in ufs_qcom_ice_program_key()
172 cfg->data_unit_size, slot); in ufs_qcom_ice_program_key()
174 return qcom_ice_evict_key(host->ice, slot); in ufs_qcom_ice_program_key()
203 if (!host->is_lane_clks_enabled) in ufs_qcom_disable_lane_clks()
206 clk_bulk_disable_unprepare(host->num_clks, host->clks); in ufs_qcom_disable_lane_clks()
208 host->is_lane_clks_enabled = false; in ufs_qcom_disable_lane_clks()
215 err = clk_bulk_prepare_enable(host->num_clks, host->clks); in ufs_qcom_enable_lane_clks()
219 host->is_lane_clks_enabled = true; in ufs_qcom_enable_lane_clks()
227 struct device *dev = host->hba->dev; in ufs_qcom_init_lane_clks()
232 err = devm_clk_bulk_get_all(dev, &host->clks); in ufs_qcom_init_lane_clks()
236 host->num_clks = err; in ufs_qcom_init_lane_clks()
270 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_qcom_check_hibern8()
274 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", in ufs_qcom_check_hibern8()
283 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); in ufs_qcom_select_unipro_mode()
285 if (host->hw_ver.major >= 0x05) in ufs_qcom_select_unipro_mode()
286 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
290 * ufs_qcom_host_reset - reset host controller and PHY
298 if (!host->core_reset) in ufs_qcom_host_reset()
301 reenable_intr = hba->is_irq_enabled; in ufs_qcom_host_reset()
304 ret = reset_control_assert(host->core_reset); in ufs_qcom_host_reset()
306 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", in ufs_qcom_host_reset()
313 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in ufs_qcom_host_reset()
318 ret = reset_control_deassert(host->core_reset); in ufs_qcom_host_reset()
320 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", in ufs_qcom_host_reset()
337 if (host->hw_ver.major >= 0x4) in ufs_qcom_get_hs_gear()
340 /* Default is HS-G3 */ in ufs_qcom_get_hs_gear()
347 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_power_up_sequence()
348 struct phy *phy = host->generic_phy; in ufs_qcom_power_up_sequence()
353 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. in ufs_qcom_power_up_sequence()
354 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, in ufs_qcom_power_up_sequence()
355 * so that the subsequent power mode change shall stick to Rate-A. in ufs_qcom_power_up_sequence()
357 if (host->hw_ver.major == 0x5) { in ufs_qcom_power_up_sequence()
358 if (host->phy_gear == UFS_HS_G5) in ufs_qcom_power_up_sequence()
359 host_params->hs_rate = PA_HS_MODE_A; in ufs_qcom_power_up_sequence()
361 host_params->hs_rate = PA_HS_MODE_B; in ufs_qcom_power_up_sequence()
364 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; in ufs_qcom_power_up_sequence()
371 /* phy initialization - calibrate the phy */ in ufs_qcom_power_up_sequence()
374 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in ufs_qcom_power_up_sequence()
379 ret = phy_set_mode_ext(phy, mode, host->phy_gear); in ufs_qcom_power_up_sequence()
383 /* power on phy - start serdes and phy's power and clocks */ in ufs_qcom_power_up_sequence()
386 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", in ufs_qcom_power_up_sequence()
403 * Internal hardware sub-modules within the UTP controller control the CGCs.
404 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
444 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); in ufs_qcom_hce_enable_notify()
445 err = -EINVAL; in ufs_qcom_hce_enable_notify()
452 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
460 * Return: zero for success and non-zero in case of a failure.
477 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) in ufs_qcom_cfg_timers()
481 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); in ufs_qcom_cfg_timers()
482 return -EINVAL; in ufs_qcom_cfg_timers()
485 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_cfg_timers()
486 if (!strcmp(clki->name, "core_clk")) { in ufs_qcom_cfg_timers()
488 core_clk_rate = clki->max_freq; in ufs_qcom_cfg_timers()
490 core_clk_rate = clk_get_rate(clki->clk); in ufs_qcom_cfg_timers()
522 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_link_startup_notify()
524 return -EINVAL; in ufs_qcom_link_startup_notify()
529 dev_err(hba->dev, "cfg core clk ctrl failed\n"); in ufs_qcom_link_startup_notify()
552 if (!host->device_reset) in ufs_qcom_device_reset_ctrl()
555 gpiod_set_value_cansleep(host->device_reset, asserted); in ufs_qcom_device_reset_ctrl()
562 struct phy *phy = host->generic_phy; in ufs_qcom_suspend()
589 struct phy *phy = host->generic_phy; in ufs_qcom_resume()
595 dev_err(hba->dev, "%s: failed PHY power on: %d\n", in ufs_qcom_resume()
615 if (host->dev_ref_clk_ctrl_mmio && in ufs_qcom_dev_ref_clk_ctrl()
616 (enable ^ host->is_dev_ref_clk_enabled)) { in ufs_qcom_dev_ref_clk_ctrl()
617 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
620 temp |= host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
622 temp &= ~host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
633 gating_wait = host->hba->dev_info.clk_gating_wait_us; in ufs_qcom_dev_ref_clk_ctrl()
641 * HS-MODE to LS-MODE or HIBERN8 state. Give it in ufs_qcom_dev_ref_clk_ctrl()
649 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
655 readl(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
665 host->is_dev_ref_clk_enabled = enable; in ufs_qcom_dev_ref_clk_ctrl()
671 struct device *dev = host->hba->dev; in ufs_qcom_icc_set_bw()
674 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); in ufs_qcom_icc_set_bw()
680 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); in ufs_qcom_icc_set_bw()
691 struct ufs_pa_layer_attr *p = &host->dev_req_params; in ufs_qcom_get_bw_table()
692 int gear = max_t(u32, p->gear_rx, p->gear_tx); in ufs_qcom_get_bw_table()
693 int lane = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_bw_table()
706 if (p->hs_rate == PA_HS_MODE_B) in ufs_qcom_get_bw_table()
730 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_pwr_change_notify()
735 return -EINVAL; in ufs_qcom_pwr_change_notify()
742 dev_err(hba->dev, "%s: failed to determine capabilities\n", in ufs_qcom_pwr_change_notify()
753 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { in ufs_qcom_pwr_change_notify()
759 if (host->phy_gear == dev_req_params->gear_tx) in ufs_qcom_pwr_change_notify()
760 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_pwr_change_notify()
762 host->phy_gear = dev_req_params->gear_tx; in ufs_qcom_pwr_change_notify()
766 if (!ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
770 if (host->hw_ver.major >= 0x4) { in ufs_qcom_pwr_change_notify()
772 dev_req_params->gear_tx, in ufs_qcom_pwr_change_notify()
777 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, in ufs_qcom_pwr_change_notify()
778 dev_req_params->pwr_rx, in ufs_qcom_pwr_change_notify()
779 dev_req_params->hs_rate, false, false)) { in ufs_qcom_pwr_change_notify()
780 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_pwr_change_notify()
787 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
791 memcpy(&host->dev_req_params, in ufs_qcom_pwr_change_notify()
797 if (ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
802 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
828 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) in ufs_qcom_apply_dev_quirks()
831 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) in ufs_qcom_apply_dev_quirks()
832 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; in ufs_qcom_apply_dev_quirks()
843 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
855 if (host->hw_ver.major == 0x2) in ufs_qcom_advertise_quirks()
856 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; in ufs_qcom_advertise_quirks()
858 if (host->hw_ver.major > 0x3) in ufs_qcom_advertise_quirks()
859 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_advertise_quirks()
861 if (of_device_is_compatible(hba->dev->of_node, "qcom,sm8550-ufshc")) in ufs_qcom_advertise_quirks()
862 hba->quirks |= UFSHCD_QUIRK_BROKEN_LSDBS_CAP; in ufs_qcom_advertise_quirks()
867 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_phy_gear()
877 host->phy_gear = host_params->hs_tx_gear; in ufs_qcom_set_phy_gear()
879 if (host->hw_ver.major < 0x4) { in ufs_qcom_set_phy_gear()
885 host->phy_gear = UFS_HS_G2; in ufs_qcom_set_phy_gear()
886 } else if (host->hw_ver.major >= 0x5) { in ufs_qcom_set_phy_gear()
887 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); in ufs_qcom_set_phy_gear()
896 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_set_phy_gear()
899 * For UFS 3.1 device and older, power up the PHY using HS-G4 in ufs_qcom_set_phy_gear()
903 host->phy_gear = UFS_HS_G4; in ufs_qcom_set_phy_gear()
910 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_host_params()
915 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); in ufs_qcom_set_host_params()
920 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_qcom_set_caps()
921 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; in ufs_qcom_set_caps()
922 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; in ufs_qcom_set_caps()
923 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_qcom_set_caps()
924 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; in ufs_qcom_set_caps()
925 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_qcom_set_caps()
929 * ufs_qcom_setup_clocks - enables/disable clocks
934 * Return: 0 on success, non-zero on failure.
963 if (ufshcd_is_hs_mode(&hba->pwr_info)) in ufs_qcom_setup_clocks()
980 ufs_qcom_assert_reset(host->hba); in ufs_qcom_reset_assert()
991 ufs_qcom_deassert_reset(host->hba); in ufs_qcom_reset_deassert()
1008 struct device *dev = host->hba->dev; in ufs_qcom_icc_init()
1011 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); in ufs_qcom_icc_init()
1012 if (IS_ERR(host->icc_ddr)) in ufs_qcom_icc_init()
1013 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), in ufs_qcom_icc_init()
1016 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); in ufs_qcom_icc_init()
1017 if (IS_ERR(host->icc_cpu)) in ufs_qcom_icc_init()
1018 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), in ufs_qcom_icc_init()
1035 * ufs_qcom_init - bind phy with controller
1041 * Return: -EPROBE_DEFER if binding fails, returns negative error
1047 struct device *dev = hba->dev; in ufs_qcom_init()
1053 return -ENOMEM; in ufs_qcom_init()
1056 host->hba = hba; in ufs_qcom_init()
1060 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); in ufs_qcom_init()
1061 if (IS_ERR(host->core_reset)) { in ufs_qcom_init()
1062 err = dev_err_probe(dev, PTR_ERR(host->core_reset), in ufs_qcom_init()
1067 /* Fire up the reset controller. Failure here is non-fatal. */ in ufs_qcom_init()
1068 host->rcdev.of_node = dev->of_node; in ufs_qcom_init()
1069 host->rcdev.ops = &ufs_qcom_reset_ops; in ufs_qcom_init()
1070 host->rcdev.owner = dev->driver->owner; in ufs_qcom_init()
1071 host->rcdev.nr_resets = 1; in ufs_qcom_init()
1072 err = devm_reset_controller_register(dev, &host->rcdev); in ufs_qcom_init()
1077 host->generic_phy = devm_phy_get(dev, "ufsphy"); in ufs_qcom_init()
1078 if (IS_ERR(host->generic_phy)) { in ufs_qcom_init()
1079 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); in ufs_qcom_init()
1088 host->device_reset = devm_gpiod_get_optional(dev, "reset", in ufs_qcom_init()
1090 if (IS_ERR(host->device_reset)) { in ufs_qcom_init()
1091 err = dev_err_probe(dev, PTR_ERR(host->device_reset), in ufs_qcom_init()
1096 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, in ufs_qcom_init()
1097 &host->hw_ver.minor, &host->hw_ver.step); in ufs_qcom_init()
1099 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; in ufs_qcom_init()
1100 host->dev_ref_clk_en_mask = BIT(26); in ufs_qcom_init()
1102 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_init()
1103 if (!strcmp(clki->name, "core_clk_unipro")) in ufs_qcom_init()
1104 clki->keep_link_active = true; in ufs_qcom_init()
1125 /* Failure is non-fatal */ in ufs_qcom_init()
1142 phy_power_off(host->generic_phy); in ufs_qcom_exit()
1143 phy_exit(host->generic_phy); in ufs_qcom_exit()
1147 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1168 if (host->hw_ver.major < 4) in ufs_qcom_set_clk_40ns_cycles()
1202 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", in ufs_qcom_set_clk_40ns_cycles()
1204 return -EINVAL; in ufs_qcom_set_clk_40ns_cycles()
1220 struct list_head *head = &hba->clk_list_head; in ufs_qcom_set_core_clk_ctrl()
1227 if (!IS_ERR_OR_NULL(clki->clk) && in ufs_qcom_set_core_clk_ctrl()
1228 !strcmp(clki->name, "core_clk_unipro")) { in ufs_qcom_set_core_clk_ctrl()
1229 if (!clki->max_freq) in ufs_qcom_set_core_clk_ctrl()
1232 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); in ufs_qcom_set_core_clk_ctrl()
1234 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); in ufs_qcom_set_core_clk_ctrl()
1246 if (host->hw_ver.major >= 4) { in ufs_qcom_set_core_clk_ctrl()
1248 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1253 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1274 struct ufs_pa_layer_attr *attr = &host->dev_req_params; in ufs_qcom_clk_scale_up_pre_change()
1277 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, in ufs_qcom_clk_scale_up_pre_change()
1278 attr->hs_rate, false, true); in ufs_qcom_clk_scale_up_pre_change()
1280 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); in ufs_qcom_clk_scale_up_pre_change()
1363 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1365 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1371 host->testbus.select_major = TSTBUS_UNIPRO; in ufs_qcom_get_default_testbus_cfg()
1372 host->testbus.select_minor = 37; in ufs_qcom_get_default_testbus_cfg()
1377 if (host->testbus.select_major >= TSTBUS_MAX) { in ufs_qcom_testbus_cfg_is_ok()
1378 dev_err(host->hba->dev, in ufs_qcom_testbus_cfg_is_ok()
1380 __func__, host->testbus.select_major); in ufs_qcom_testbus_cfg_is_ok()
1394 return -EINVAL; in ufs_qcom_testbus_config()
1397 return -EPERM; in ufs_qcom_testbus_config()
1399 switch (host->testbus.select_major) { in ufs_qcom_testbus_config()
1456 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1457 (u32)host->testbus.select_major << 19, in ufs_qcom_testbus_config()
1459 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1460 (u32)host->testbus.select_minor << offset, in ufs_qcom_testbus_config()
1493 /* clear bit 17 - UTP_DBG_RAMS_EN */ in ufs_qcom_dump_dbg_regs()
1519 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1520 * @hba: per-adapter instance
1529 if (!host->device_reset) in ufs_qcom_device_reset()
1530 return -EOPNOTSUPP; in ufs_qcom_device_reset()
1550 p->polling_ms = 60; in ufs_qcom_config_scaling_param()
1551 p->timer = DEVFREQ_TIMER_DELAYED; in ufs_qcom_config_scaling_param()
1552 d->upthreshold = 70; in ufs_qcom_config_scaling_param()
1553 d->downdifferential = 5; in ufs_qcom_config_scaling_param()
1555 hba->clk_scaling.suspend_on_no_request = true; in ufs_qcom_config_scaling_param()
1569 phy_power_off(host->generic_phy); in ufs_qcom_reinit_notify()
1590 struct platform_device *pdev = to_platform_device(hba->dev); in ufs_qcom_mcq_config_resource()
1595 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); in ufs_qcom_mcq_config_resource()
1598 res = &hba->res[i]; in ufs_qcom_mcq_config_resource()
1599 res->resource = platform_get_resource_byname(pdev, in ufs_qcom_mcq_config_resource()
1601 res->name); in ufs_qcom_mcq_config_resource()
1602 if (!res->resource) { in ufs_qcom_mcq_config_resource()
1603 dev_info(hba->dev, "Resource %s not provided\n", res->name); in ufs_qcom_mcq_config_resource()
1605 return -ENODEV; in ufs_qcom_mcq_config_resource()
1608 res_mem = res->resource; in ufs_qcom_mcq_config_resource()
1609 res->base = hba->mmio_base; in ufs_qcom_mcq_config_resource()
1613 res->base = devm_ioremap_resource(hba->dev, res->resource); in ufs_qcom_mcq_config_resource()
1614 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1615 dev_err(hba->dev, "Failed to map res %s, err=%d\n", in ufs_qcom_mcq_config_resource()
1616 res->name, (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1617 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1618 res->base = NULL; in ufs_qcom_mcq_config_resource()
1624 res = &hba->res[RES_MCQ]; in ufs_qcom_mcq_config_resource()
1626 if (res->base) in ufs_qcom_mcq_config_resource()
1630 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); in ufs_qcom_mcq_config_resource()
1632 return -ENOMEM; in ufs_qcom_mcq_config_resource()
1634 res_mcq->start = res_mem->start + in ufs_qcom_mcq_config_resource()
1635 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); in ufs_qcom_mcq_config_resource()
1636 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; in ufs_qcom_mcq_config_resource()
1637 res_mcq->flags = res_mem->flags; in ufs_qcom_mcq_config_resource()
1638 res_mcq->name = "mcq"; in ufs_qcom_mcq_config_resource()
1642 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", in ufs_qcom_mcq_config_resource()
1647 res->base = devm_ioremap_resource(hba->dev, res_mcq); in ufs_qcom_mcq_config_resource()
1648 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1649 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", in ufs_qcom_mcq_config_resource()
1650 (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1651 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1656 hba->mcq_base = res->base; in ufs_qcom_mcq_config_resource()
1659 res->base = NULL; in ufs_qcom_mcq_config_resource()
1670 mem_res = &hba->res[RES_UFS]; in ufs_qcom_op_runtime_config()
1671 sqdao_res = &hba->res[RES_MCQ_SQD]; in ufs_qcom_op_runtime_config()
1673 if (!mem_res->base || !sqdao_res->base) in ufs_qcom_op_runtime_config()
1674 return -EINVAL; in ufs_qcom_op_runtime_config()
1677 opr = &hba->mcq_opr[i]; in ufs_qcom_op_runtime_config()
1678 opr->offset = sqdao_res->resource->start - in ufs_qcom_op_runtime_config()
1679 mem_res->resource->start + 0x40 * i; in ufs_qcom_op_runtime_config()
1680 opr->stride = 0x100; in ufs_qcom_op_runtime_config()
1681 opr->base = sqdao_res->base + 0x40 * i; in ufs_qcom_op_runtime_config()
1696 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; in ufs_qcom_get_outstanding_cqs()
1698 if (!mcq_vs_res->base) in ufs_qcom_get_outstanding_cqs()
1699 return -EINVAL; in ufs_qcom_get_outstanding_cqs()
1701 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); in ufs_qcom_get_outstanding_cqs()
1719 u32 id = desc->msi_index; in ufs_qcom_mcq_esi_handler()
1720 struct ufs_hw_queue *hwq = &hba->uhq[id]; in ufs_qcom_mcq_esi_handler()
1735 if (host->esi_enabled) in ufs_qcom_config_esi()
1742 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; in ufs_qcom_config_esi()
1743 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, in ufs_qcom_config_esi()
1746 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); in ufs_qcom_config_esi()
1750 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1751 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1752 ret = devm_request_irq(hba->dev, desc->irq, in ufs_qcom_config_esi()
1754 IRQF_SHARED, "qcom-mcq-esi", desc); in ufs_qcom_config_esi()
1756 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", in ufs_qcom_config_esi()
1757 __func__, desc->irq, ret); in ufs_qcom_config_esi()
1762 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1766 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1767 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1770 devm_free_irq(hba->dev, desc->irq, hba); in ufs_qcom_config_esi()
1772 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1773 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_config_esi()
1775 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && in ufs_qcom_config_esi()
1776 host->hw_ver.step == 0) in ufs_qcom_config_esi()
1778 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), in ufs_qcom_config_esi()
1781 host->esi_enabled = true; in ufs_qcom_config_esi()
1788 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1819 * ufs_qcom_probe - probe routine of the driver
1822 * Return: zero for success and non-zero for failure.
1827 struct device *dev = &pdev->dev; in ufs_qcom_probe()
1838 * ufs_qcom_remove - set driver_data of the device to NULL
1847 pm_runtime_get_sync(&(pdev)->dev); in ufs_qcom_remove()
1849 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_remove()
1854 { .compatible = "qcom,sm8550-ufshc" },
1884 .name = "ufshcd-qcom",