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/linux/drivers/fpga/
H A Dmachxo2-spi.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/delay.h>
12 #include <linux/fpga/fpga-mgr.h>
18 /* MachXO2 Programming Guide - sysCONFIG Programming Commands */
30 * Sheet' sysCONFIG Port Timing Specifications (3-36)
69 struct spi_transfer rx, tx; in get_status() local
74 memset(&tx, 0, sizeof(tx)); in get_status()
75 tx.tx_buf = cmd; in get_status()
76 tx.len = sizeof(cmd); in get_status()
80 spi_message_add_tail(&tx, &msg); in get_status()
[all …]
/linux/drivers/iio/imu/
H A Dadis.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/delay.h>
27 * __adis_write_reg() - write N bytes to register (unlocked version)
41 .tx_buf = adis->tx, in __adis_write_reg()
44 .delay.value = adis->data->write_delay, in __adis_write_reg()
45 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
47 .tx_buf = adis->tx + 2, in __adis_write_reg()
50 .delay.value = adis->data->write_delay, in __adis_write_reg()
51 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
H A Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
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H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
/linux/drivers/spi/
H A Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
[all …]
H A Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
15 #include <linux/delay.h>
18 #include <linux/spi/spi-mem.h>
23 #include "spi-dw.h"
32 u32 rx_sample_dly; /* RX sample delay */
66 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
67 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
69 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
19 $ref: /schemas/types.yaml#/definitions/uint32-array
21 - description: Delay between rts signal and beginning of data sent in
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/linux/arch/mips/boot/dts/cavium-octeon/
H A Dubnt_e100.dts1 // SPDX-License-Identifier: GPL-2.0-only
15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
32 phy-handle = <&phy7>;
33 rx-delay = <0>;
34 tx-delay = <0x10>;
[all …]
/linux/Documentation/networking/
H A Dpktgen.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
31 overload type of benchmarking, as this could hurt the normal use-case.
33 Specifically increasing the TX ring buffer in the NIC::
35 # ethtool -G ethX tx 1024
37 A larger TX ring can improve pktgen's performance, while it can hurt
38 in the general case, 1) because the TX ring buffer might get larger
43 TX ring cause delay. Drivers usually delay cleaning up the
44 ring-buffers for various performance reasons, and packets stalling
45 the TX ring might just be waiting for cleanup.
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* N-PHY registers. */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
58 #define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
116 #define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
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/linux/drivers/isdn/mISDN/
H A Ddsp_cmx.c20 * There are 3 different solutions: -1 = software, 0 = hardware-crossconnect
21 * 1-n = hardware-conference. The n will give the conference number.
39 * - Crossconnecting or even conference, if more than two members are together.
40 * - Force mixing of transmit data with other crossconnect/conference members.
41 * - Echo generation to benchmark the delay of audio processing.
42 * - Use hardware to minimize cpu load, disable FIFO load and minimize delay.
43 * - Dejittering and clock generation.
48 * RX-Buffer
51 * ----------------+-------------+-------------------
53 * The rx-buffer is a ring buffer used to store the received data for each
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Drenesas,sh-msiof.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
17 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
19 - items:
20 - enum:
[all …]
H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
12 be controller specific like delay in clock or data lines, etc. These
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
[all …]
/linux/net/nfc/nci/
H A Dspi.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/crc-ccitt.h>
39 t.tx_buf = skb->data; in __nci_spi_send()
40 t.len = skb->len; in __nci_spi_send()
47 t.delay.value = nspi->xfer_udelay; in __nci_spi_send()
48 t.delay.unit = SPI_DELAY_UNIT_USECS; in __nci_spi_send()
49 t.speed_hz = nspi->xfer_speed_hz; in __nci_spi_send()
54 return spi_sync(nspi->spi, &m); in __nci_spi_send()
61 unsigned int payload_len = skb->len; in nci_spi_send()
69 hdr[1] = nspi->acknowledge_mode; in nci_spi_send()
[all …]
/linux/include/linux/amba/
H A Dpl022.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2008-2009 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
31 * enum ssp_interface - interfaces allowed for this SSP Controller
48 * enum ssp_hierarchy - whether SSP is configured as Master or Slave
56 * enum ssp_clock_params - clock parameters, to set SSP clock at a
65 * enum ssp_rx_endian - endianess of Rx FIFO Data
74 * enum ssp_tx_endian - endianess of Tx FIFO Data
82 * enum ssp_data_size - number of bits in one data element
98 * enum ssp_mode - SSP mode of operation (Communication modes)
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]
/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
23 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
71 #define PHY_AR8031_SERDES_TX_CLK_DLY 0x0100 /* TX clock delay of 2.0ns */
84 #define PHY_NEXT_PAGE_TX_DEFAULT 0x2001 /* Next Page TX */
85 #define PHY_1000T_CTRL_DEFAULT 0x0300 /* 1000Base-T Control Register */
89 * pch_gbe_phy_get_id - Retrieve the PHY ID and revision
[all …]

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