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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_tmds_clk.c69 struct sun4i_tmds *tmds = hw_to_tmds(hw); in sun4i_tmds_determine_rate() local
88 for (j = tmds->div_offset ?: 1; in sun4i_tmds_determine_rate()
89 j < (16 + tmds->div_offset); j++) { in sun4i_tmds_determine_rate()
128 struct sun4i_tmds *tmds = hw_to_tmds(hw); in sun4i_tmds_recalc_rate() local
131 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); in sun4i_tmds_recalc_rate()
135 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); in sun4i_tmds_recalc_rate()
136 reg = ((reg >> 4) & 0xf) + tmds->div_offset; in sun4i_tmds_recalc_rate()
146 struct sun4i_tmds *tmds = hw_to_tmds(hw); in sun4i_tmds_set_rate() local
151 sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset, in sun4i_tmds_set_rate()
154 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); in sun4i_tmds_set_rate()
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H A Dsun8i_dw_hdmi.c136 hdmi->clk_tmds = devm_clk_get(dev, "tmds"); in sun8i_dw_hdmi_bind()
139 "Couldn't get the tmds clock\n"); in sun8i_dw_hdmi_bind()
160 dev_err(dev, "Could not enable tmds clock\n"); in sun8i_dw_hdmi_bind()
/linux/drivers/gpu/drm/display/
H A Ddrm_scdc_helper.c175 * Writes the TMDS config register over SCDC channel, and:
191 "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", in drm_scdc_set_scrambling()
214 * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
219 * TMDS clock ratio calculations go like this:
220 * TMDS character = 10 bit TMDS encoded value
222 * TMDS character rate = The rate at which TMDS characters are
225 * TMDS bit rate = 10x TMDS character rate
228 * TMDS clock rate for pixel clock < 340 MHz = 1x the character
231 * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
234 * Writes to the TMDS config register over SCDC channel, and:
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H A Ddrm_dp_dual_mode_helper.c262 * drm_dp_dual_mode_max_tmds_clock - Max TMDS clock for DP dual mode adaptor
267 * Determine the max TMDS clock the adaptor supports based on the
275 * Maximum supported TMDS clock rate for the DP dual mode adaptor in kHz.
297 drm_dbg_kms(dev, "Failed to query max TMDS clock\n"); in drm_dp_dual_mode_max_tmds_clock()
306 …* drm_dp_dual_mode_get_tmds_output - Get the state of the TMDS output buffers in the DP dual mode …
310 * @enabled: current state of the TMDS output buffers
312 * Get the state of the TMDS output buffers in the adaptor. For
337 drm_dbg_kms(dev, "Failed to query state of TMDS output buffers\n"); in drm_dp_dual_mode_get_tmds_output()
348 * drm_dp_dual_mode_set_tmds_output - Enable/disable TMDS output buffers in the DP dual mode adaptor
352 * @enable: enable (as opposed to disable) the TMDS output buffers
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H A Ddrm_hdmi_helper.c200 * drm_hdmi_compute_mode_clock() - Computes the TMDS Character Rate
205 * Returns the TMDS Character Rate for a given mode, bpc count and output format.
208 * The TMDS Character Rate, in Hertz, or 0 on error.
238 * three TMDS channels per pixel clock, which is equivalent to in drm_hdmi_compute_mode_clock()
247 * specifies that YUV420 encoding is carried at a TMDS Character Rate in drm_hdmi_compute_mode_clock()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_combios.c94 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
95 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
339 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ in combios_get_table_offset()
348 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ in combios_get_table_offset()
1300 struct radeon_encoder_int_tmds *tmds) in radeon_legacy_get_tmds_info_from_table() argument
1307 tmds->tmds_pll[i].value = in radeon_legacy_get_tmds_info_from_table()
1309 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; in radeon_legacy_get_tmds_info_from_table()
1316 struct radeon_encoder_int_tmds *tmds) in radeon_legacy_get_tmds_info_from_combios() argument
1334 tmds->tmds_pll[i].value = in radeon_legacy_get_tmds_info_from_combios()
1336 tmds->tmds_pll[i].freq = in radeon_legacy_get_tmds_info_from_combios()
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H A Dradeon_legacy_encoders.c796 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; in radeon_legacy_tmds_int_mode_set() local
799 if (tmds->tmds_pll[i].freq == 0) in radeon_legacy_tmds_int_mode_set()
801 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { in radeon_legacy_tmds_int_mode_set()
802 tmp = tmds->tmds_pll[i].value ; in radeon_legacy_tmds_int_mode_set()
1695 struct radeon_encoder_int_tmds *tmds; in radeon_legacy_get_tmds_info() local
1698 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); in radeon_legacy_get_tmds_info()
1700 if (!tmds) in radeon_legacy_get_tmds_info()
1704 ret = radeon_atombios_get_tmds_info(encoder, tmds); in radeon_legacy_get_tmds_info()
1706 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); in radeon_legacy_get_tmds_info()
1709 radeon_legacy_get_tmds_info_from_table(encoder, tmds); in radeon_legacy_get_tmds_info()
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H A Dradeon_mode.h253 /* legacy TMDS PLL detect */
405 /* legacy int tmds */
410 /* tmds over dvo */
853 struct radeon_encoder_int_tmds *tmds);
855 struct radeon_encoder_int_tmds *tmds);
857 struct radeon_encoder_int_tmds *tmds);
859 struct radeon_encoder_ext_tmds *tmds);
861 struct radeon_encoder_ext_tmds *tmds);
/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi.h47 * @clk_tmds: hdmi tmds clock
97 * A pointer to an array of these structures is passed to a TMDS (HDMI) output
100 * specific configuration for a given TMDS clock frequency range.
102 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to
103 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to
H A Dsti_hdmi_tx3g4c28phy.c96 DRM_ERROR("input TMDS clock speed (%d) not supported\n", in sti_hdmi_tx3g4c28phy_start()
106 DRM_ERROR("output TMDS clock (%d) out of range\n", tmdsck); in sti_hdmi_tx3g4c28phy_start()
143 * for different high speed TMDS clock frequencies a phy configuration in sti_hdmi_tx3g4c28phy_start()
/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-dw-hdmi.yaml20 - A custom HDMI PHY in order to convert video to TMDS signal
25 | Synopsys HDMI | HDMI PHY |=> TMDS
98 A port node pointing to the TMDS Output port node.
149 /* TMDS Output */
H A Dallwinner,sun8i-a83t-dw-hdmi.yaml52 - description: TMDS Clock
62 - const: tmds
170 clock-names = "iahb", "isfr", "tmds";
227 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
/linux/include/media/i2c/
H A Dtc358743.h80 /* Reset PHY automatically when TMDS clock goes from DC to AC.
86 /* Reset PHY automatically when TMDS clock passes 21 MHz.
92 /* Reset PHY automatically when TMDS clock is detected.
/linux/drivers/gpu/drm/i2c/
H A DKconfig16 tristate "Silicon Image sil164 TMDS transmitter"
20 when used in pairs) TMDS transmitters, used in some nVidia
/linux/drivers/video/fbdev/via/
H A Dchip.h64 /* Definition TMDS Trasmitter Information */
67 /* Definition TMDS Trasmitter Index */
72 /* Definition TMDS Trasmitter I2C Target Address */
H A Ddvi.c81 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n"); in viafb_tmds_trasmitter_identify()
91 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n"); in viafb_tmds_trasmitter_identify()
107 DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n"); in viafb_tmds_trasmitter_identify()
317 /* Turn off TMDS power. */ in viafb_dvi_disable()
455 /* Turn on TMDS power. */ in viafb_dvi_enable()
/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8195.c33 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G, in mtk_phy_tmds_clk_ratio()
233 * 0M < TMDS clk < 54M /8 in mtk_hdmi_pll_calc()
234 * 54M <= TMDS clk < 148.35M /4 in mtk_hdmi_pll_calc()
235 * 148.35M <=TMDS clk < 296.7M /2 in mtk_hdmi_pll_calc()
236 * 296.7 <=TMDS clk <= 594M /1 in mtk_hdmi_pll_calc()
321 /* 3G < data rate <= 6G, 300M < tmds rate <= 594M */ in mtk_hdmi_pll_drv_setting()
/linux/drivers/gpu/drm/tests/
H A Ddrm_connector_test.c989 * Test that for a given mode, with 8bpc and an RGB output the TMDS
1010 * Test that for a given mode, with 10bpc and an RGB output the TMDS
1031 * Test that for the VIC-1 mode, with 10bpc and an RGB output the TMDS
1049 * Test that for a given mode, with 12bpc and an RGB output the TMDS
1070 * Test that for the VIC-1 mode, with 12bpc and an RGB output the TMDS
1088 * Test that for a mode with the pixel repetition flag, the TMDS
1109 * Test that the TMDS character rate computation for the VIC modes
1146 * with 10bpc, the TMDS character rate is equal to 0.625 times the mode
1171 * with 12bpc, the TMDS character rate is equal to 0.75 times the mode
1195 * Test that for a given mode, the computation of the TMDS character
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H A Ddrm_kunit_edid.h28 * DFP 1.x compatible TMDS
95 * DFP 1.x compatible TMDS
137 * Maximum TMDS clock: 200 MHz
197 * DFP 1.x compatible TMDS
239 * Maximum TMDS clock: 340 MHz
299 * DFP 1.x compatible TMDS
347 * Maximum TMDS clock: 200 MHz
407 * DFP 1.x compatible TMDS
455 * Maximum TMDS clock: 340 MHz
H A Ddrm_hdmi_state_helper_test.c900 * Test that when doing a commit which would use RGB 8bpc, the TMDS
946 * Test that when doing a commit which would use RGB 10bpc, the TMDS
993 * Test that when doing a commit which would use RGB 12bpc, the TMDS
1094 * - The chosen mode has a TMDS character rate higher than the display
1096 * - The chosen mode has a TMDS character rate lower than the display
1099 * Then we will pick the latter, and the computed TMDS character rate
1160 * - The chosen mode has a TMDS character rate higher than the display
1163 * - The chosen mode has a TMDS character rate lower than the display
1332 * because the TMDS character rate exceeds the maximum supported in drm_test_check_output_bpc_format_driver_rgb_only()
1399 * because the TMDS character rate exceeds the maximum supported in drm_test_check_output_bpc_format_display_rgb_only()
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bios.c144 * conf byte. These tables are similar to the TMDS tables, consisting in run_lvds_table()
630 * This runs the TMDS regs setting code found on BIT bios cards in run_tmds_table()
643 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ in run_tmds_table()
650 clktable = bios->tmds.output0_script_ptr; in run_tmds_table()
654 clktable = bios->tmds.output1_script_ptr; in run_tmds_table()
666 NV_ERROR(drm, "TMDS output init script not found\n"); in run_tmds_table()
905 * Parses the pointer to the TMDS table in parse_bit_tmds_tbl_entry()
909 * offset + 0 (16 bits): TMDS table pointer in parse_bit_tmds_tbl_entry()
911 * The TMDS table is typically found just before the DCB table, with a in parse_bit_tmds_tbl_entry()
931 NV_ERROR(drm, "Do not understand BIT TMDS table\n"); in parse_bit_tmds_tbl_entry()
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgm200.c78 ior->tmds.high_speed = khz > 340000; in gm200_sor_hdmi_scdc()
81 if (ior->tmds.high_speed) in gm200_sor_hdmi_scdc()
83 if (ior->tmds.high_speed || scrambling_low_rates) in gm200_sor_hdmi_scdc()
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h104 * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
141 * used when TMDS CLK rate = TMDS character rate /4. Default 0.
/linux/drivers/gpu/drm/tegra/
H A Dhdmi.c52 const struct tmds_config *tmds; member
835 const struct tmds_config *tmds) in tegra_hdmi_setup_tmds() argument
839 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); in tegra_hdmi_setup_tmds()
840 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); in tegra_hdmi_setup_tmds()
841 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT); in tegra_hdmi_setup_tmds()
843 tegra_hdmi_writel(hdmi, tmds->drive_current, in tegra_hdmi_setup_tmds()
851 tegra_hdmi_writel(hdmi, tmds->peak_current, in tegra_hdmi_setup_tmds()
1333 /* TMDS CONFIG */ in tegra_hdmi_encoder_enable()
1335 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) { in tegra_hdmi_encoder_enable()
1336 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]); in tegra_hdmi_encoder_enable()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-anx78xx.h104 * TMDS Control
107 /* TMDS Control Registers */
109 /* Bits for TMDS Control Register 7 */

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