/freebsd/sys/contrib/device-tree/Bindings/timer/ |
H A D | ti,timer.txt | 1 OMAP Timer bindings 4 - compatible: Should be set to one of the below. Please note that 5 OMAP44xx devices have timer instances that are 100% 8 So for OMAP44xx devices timer instances may use 11 ti,omap2420-timer (applicable to OMAP24xx devices) 12 ti,omap3430-timer (applicable to OMAP3xxx/44xx devices) 13 ti,omap4430-timer (applicable to OMAP44xx devices) 14 ti,omap5430-timer (applicable to OMAP543x devices) 15 ti,am335x-timer (applicable to AM335x devices) 16 ti,am335x-timer-1ms (applicable to AM335x devices) [all …]
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H A D | ti,timer-dm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI dual-mode timer 10 - Tony Lindgren <tony@atomide.com> 13 The TI dual-mode timer is a general purpose timer with PWM capabilities. 18 - items: 19 - enum: 20 - ti,am335x-timer [all …]
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H A D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ARM architected timer 10 - Marc Zyngier <marc.zyngier@arm.com> 11 - Mark Rutland <mark.rutland@arm.com> 13 ARM cores may have a per-core architected timer, which provides per-cpu timers, 14 or a memory mapped architected timer, which provides up to 8 frames with a 15 physical and optional virtual timer per frame. [all …]
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/freebsd/sys/contrib/openzfs/man/man8/ |
H A D | zpool-trim.8 | 9 .\" or https://opensource.org/licenses/CDDL-1.0. 27 .\" Copyright (c) 2017 Open-E, Inc. All Rights Reserved. 34 .Nm zpool-trim 46 Initiates an immediate on-demand TRIM operation for all of the free space in 52 A manual on-demand TRIM operation can be initiated irrespective of the 58 .Bl -tag -width Ds 59 .It Fl d , -secure 60 Causes a secure TRIM to be initiated. 61 When performing a secure TRIM, the 64 .It Fl r , -rate Ar rate [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/arm/ |
H A D | corstone1000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 interrupt-parent = <&gic>; 12 #address-cells = <1>; 13 #size-cells = <1>; 21 stdout-pat [all...] |
/freebsd/sys/contrib/device-tree/Bindings/arm/ |
H A D | atmel-sysregs.txt | 4 - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" 5 - reg : Should contain registers location and length 7 PIT Timer required properties: 8 - compatible: Should be "atmel,at91sam9260-pit" 9 - reg: Should contain registers location and length 10 - interrupts: Should contain interrupt for the PIT which is the IRQ line 13 PIT64B Timer required properties: 14 - compatible: Should be "microchip,sam9x60-pit64b" 15 - reg: Should contain registers location and length 16 - interrupts: Should contain interrupt for PIT64B timer [all …]
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/freebsd/sys/arm/include/ |
H A D | sysreg.h | 1 /*- 31 * Note that when register r0 is hard-coded in these definitions it means the 33 * because some syntatically-valid register name has to appear at that point to 96 #define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */ 97 #define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */ 98 #define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */ 170 #define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ 171 #define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ 172 #define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged r… 173 #define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged w… [all …]
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/freebsd/sys/arm/arm/ |
H A D | generic_timer.c | 1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 36 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer 89 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */ 90 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */ 125 .name = "sec-phys", 140 .name = "hyp-phys", 145 .name = "hyp-virt", 275 /* Always enable the virtual timer */ in setup_user_access() 277 /* Enable the physical timer if supported */ in setup_user_access() [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/intel/ |
H A D | keembay-soc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 16 #address-cells = <1>; 17 #size-cells = <0>; 20 compatible = "arm,cortex-a53"; 23 enable-method = "psci"; 27 compatible = "arm,cortex-a53"; [all …]
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H A D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 7 #include <dt-bindings/reset/altr,rst-mgr-s10.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controlle [all...] |
/freebsd/sys/contrib/device-tree/Bindings/rtc/ |
H A D | rtc-meson-vrtc.txt | 8 - compatible: should be "amlogic,meson-vrtc" 9 - reg: physical address for the alarm register 12 application processors (AP) and the secure co-processor (SCP.) When 14 program an always-on timer before going sleep. When the timer expires, 20 compatible = "amlogic,meson-vrtc";
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H A D | amlogic,meson-vrtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/amlogic,meson-vrtc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Neil Armstrong <neil.armstrong@linaro.org> 17 application processors (AP) and the secure co-processor (SCP.) When 19 program an always-on timer before going sleep. When the timer expires, 23 - $ref: rtc.yaml# 28 - amlogic,meson-vrtc 34 - compatible [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/tesla/ |
H A D | fsd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Tesla Full Self-Driving SoC device tree source 5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2017-2022 Tesla, Inc. 11 #include <dt-bindings/clock/fsd-clk.h> 12 #include <dt-bindings/interrupt-controlle [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/altera/ |
H A D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 /dts-v1/; 7 #include <dt-bindings/reset/altr,rst-mgr-s10.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-binding [all...] |
/freebsd/sys/contrib/device-tree/include/dt-bindings/gce/ |
H A D | mt8186-gce.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 79 /* VCU: poll with timeout for GPR timer */ 351 * Note that token 512 to 639 may set secure 367 /* Notify normal CMDQ there are some secure task done 368 * MUST NOT CHANGE, this token sync with secure world 386 * There are 15 32-bit GPR, 3 GPR form a set 387 * (64-bit for address, 32-bit for value) 400 /* event for gpr timer, used in sleep and poll with timeout */
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8dxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/clock/imx8-clock.h> 7 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gi [all...] |
H A D | imx8qm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controlle [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/nuvoton/ |
H A D | ma35d1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 * Author: Shan-Chun Hung <schung@nuvoton.com> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> 12 #include <dt-bindings/reset/nuvoton,ma35d1-reset.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; [all …]
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/freebsd/contrib/ntp/sntp/libevent/include/event2/ |
H A D | util.h | 2 * Copyright (c) 2007-2012 Niels Provos and Nick Mathewson 31 Common convenience functions for cross-platform portability and 41 #include <event2/event-config.h> 88 * C99-specified stdint.h. Shamefully, some platforms do not include 203 /* Note that we define ev_off_t based on the compile-time size of off_t that 226 - The compiler does constant folding properly. 227 - The platform does signed arithmetic in two's complement. 241 #define EV_INT64_MIN ((-EV_INT64_MAX) - 1) 244 #define EV_INT32_MIN ((-EV_INT32_MAX) - 1) 247 #define EV_INT16_MIN ((-EV_INT16_MAX) - 1) [all …]
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/freebsd/contrib/libevent/include/event2/ |
H A D | util.h | 2 * Copyright (c) 2007-2012 Niels Provos and Nick Mathewson 31 Common convenience functions for cross-platform portability and 41 #include <event2/event-config.h> 88 * C99-specified stdint.h. Shamefully, some platforms do not include 203 /* Note that we define ev_off_t based on the compile-time size of off_t that 226 - The compiler does constant folding properly. 227 - The platform does signed arithmetic in two's complement. 241 #define EV_INT64_MIN ((-EV_INT64_MAX) - 1) 244 #define EV_INT32_MIN ((-EV_INT32_MAX) - 1) 247 #define EV_INT16_MIN ((-EV_INT16_MAX) - 1) [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/ti/ |
H A D | k3-j7200-mcu-wakeup.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 13 mbox-names = "rx", "tx"; 18 reg-name [all...] |
H A D | k3-j721s2-mcu-wakeup.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 13 mbox-names = "rx", "tx"; 18 reg-names = "debug_messages"; 21 k3_pds: power-controlle [all...] |
H A D | k3-j784s4-mcu-wakeup.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 9 sms: system-controller@44083000 { 10 bootph-all; 11 compatible = "ti,k2g-sci"; 12 ti,host-id = <12>; 14 mbox-names = "rx", "tx"; 19 reg-name [all...] |
/freebsd/sys/arm64/conf/ |
H A D | std.allwinner | 10 # Timer drivers 31 # Real-time clock support 32 device aw_rtc # Allwinner Real-time Clock 41 device axp81x # X-Powers AXP81x PMIC 44 device aw_sid # Allwinner Secure ID EFUSE
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/freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
H A D | intel,keembay-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/watchdog/intel,keembay-wd [all...] |