Lines Matching +full:timer +full:- +full:secure

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10   - Marc Zyngier <marc.zyngier@arm.com>
11   - Mark Rutland <mark.rutland@arm.com>
13   ARM cores may have a per-core architected timer, which provides per-cpu timers,
14   or a memory mapped architected timer, which provides up to 8 frames with a
15   physical and optional virtual timer per frame.
17   The per-core architected timer is attached to a GIC to deliver its
18   per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24       - items:
25           - const: arm,cortex-a15-timer
26           - const: arm,armv7-timer
27       - items:
28           - enum:
29               - arm,armv7-timer
30               - arm,armv8-timer
31       - items:
32           - const: arm,armv8-timer
33           - const: arm,armv7-timer
38       - description: secure timer irq
39       - description: non-secure timer irq
40       - description: virtual timer irq
41       - description: hypervisor timer irq
42       - description: hypervisor virtual timer irq
44   interrupt-names:
46       - minItems: 2
48           - const: phys
49           - const: virt
50           - const: hyp-phys
51           - const: hyp-virt
52       - minItems: 3
54           - const: sec-phys
55           - const: phys
56           - const: virt
57           - const: hyp-phys
58           - const: hyp-virt
60   clock-frequency:
66   always-on:
68     description: If present, the timer is powered through an always-on power
71   allwinner,erratum-unknown1:
77   fsl,erratum-a008585:
79     description: Indicates the presence of QorIQ erratum A-008585, which says
81       by back-to-back reads. This also affects writes to the tval register, due
84   hisilicon,erratum-161010101:
91   arm,cpu-registers-not-fw-configured:
93     description: Firmware does not initialize any of the generic timer CPU
94       registers, which contain their architecturally-defined reset values. Only
95       supported for 32-bit systems which follow the ARMv7 architected reset
98   arm,no-tick-in-suspend:
101       low-power system suspend on some SoCs. This behavior does not match the
103       be implemented in an always-on power domain."
106   - compatible
111   - required:
112       - interrupts
113   - required:
114       - interrupts-extended
117   - |
118     timer {
119       compatible = "arm,cortex-a15-timer",
120              "arm,armv7-timer";
125       clock-frequency = <100000000>;