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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dcs35l35.txt5 - compatible : "cirrus,cs35l35"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - interrupts : IRQ line info CS35L35.
14 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - cirrus,boost-ind-nanohenr
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/freebsd/sys/dev/isci/scil/
H A Dscic_sds_ssp_request.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
78 * to determine if the RAW task management frame was sent successfully.
79 * If the raw frame was sent successfully, then the state for the
80 * task request transitions to waiting for a response frame.
111 &this_request->started_substate_machine, in scic_sds_ssp_task_request_await_tc_completion_tc_completion_handler()
124 "TaskRequest:0x%x CompletionCode:%x - ACK/NAK timeout\n", in scic_sds_ssp_task_request_await_tc_completion_tc_completion_handler()
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H A Dscic_sds_smp_request.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
98 (((POINTER_UINT)(address)) + (sizeof(U32) - 1)) \
99 & ~(sizeof(U32)- 1) \
103 * This macro returns the DWORD-aligned smp command buffer
124 (((POINTER_UINT)(address)) + (sizeof(U32) - 1)) \
125 & ~(sizeof(U32)- 1) \
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H A Dscic_sds_request.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
85 * management request to be performed in the STARTED super-state.
90 * The AWAIT_TC_COMPLETION sub-state indicates that the started raw
92 * initial frame (i.e. command, task, etc.).
97 * This sub-state indicates that the started task management request
98 * is waiting for the reception of an unsolicited frame
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kFrameLowering.h1 //===-- M68kFrameLowering.h - Define frame lowering for M68k ----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
39 /// If we're forcing a stack realignment we can't rely on just the frame
41 /// call out. Otherwise just make sure we have some alignment - we'll go
45 /// Adjusts the stack pointer using LEA, SUB, or ADD.
51 /// Aligns the stack pointer by ANDing it with -MaxAlign.
72 /// call frame setup and destroy pseudo instructions (but only if the Target
75 /// implemented if using call frame setup/destroy pseudo instructions.
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/freebsd/crypto/openssl/crypto/aes/asm/
H A Daes-ppc.pl2 # Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
20 # 128-bit key, which is ~40% better than 64-bit code generated by gcc
23 # at 1/2 of ppc_AES_encrypt speed, while ppc_AES_decrypt_compact -
32 # 4 load instructions in two cycles, only in 3. As result non-compact
37 # ppc_AES_decrypt_compact - at 55 (in 64-bit build).
61 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
62 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
63 die "can't locate ppc-xlate.pl";
68 $FRAME=32*$SIZE_T;
70 sub _data_word()
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/freebsd/crypto/openssl/crypto/rc4/asm/
H A Drc4-parisc.pl2 # Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved.
17 # RC4 for PA-RISC.
21 # Performance is 33% better than gcc 3.2 generated code on PA-7100LC.
23 # It's possible to unroll loop 8 times on PA-RISC 2.0, but improvement
26 # Special thanks to polarhome.com for providing HP-UX account.
57 $FRAME=4*$SIZE_T+$FRAME_MARKER; # 4 saved regs + frame marker
75 } else { # RC4_INT (~5% faster than RC4_CHAR on PA-7100LC)
100 sub unrolledloopbody {
113 `sprintf("%sdep %$dat1,%d,8,%$acc",$i==1?"z":"",8*($i-1)+7) if ($i>0)`
123 sub foldedloop {
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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha1-ppc.pl2 # Copyright 2006-2020 The OpenSSL Project Authors. All Rights Reserved.
22 # anybody know if pre-POWER3 can sustain unaligned load?
24 # -m64 -m32
25 # ----------------------------------
26 # PPC970,gcc-4.0.0 +76% +59%
27 # Power6,xlc-7 +68% +33%
55 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
56 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
57 die "can't locate ppc-xlate.pl";
62 $FRAME=24*$SIZE_T+64;
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H A Dsha512-parisc.pl2 # Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved.
17 # SHA256/512 block procedure for PA-RISC.
22 # PA-7100LC. Compared to code generated by vendor compiler this
23 # implementation is almost 70% faster in 64-bit build, but delivers
24 # virtually same performance in 32-bit build on PA-8600.
27 # PA-7100LC, PA-RISC 1.1 processor. Then implementation detects if the
28 # code is executed on PA-RISC 2.0 processor and switches to 64-bit
29 # code path delivering adequate performance even in "blended" 32-bit
30 # build. Though 64-bit code is not any faster than code generated by
31 # vendor compiler on PA-8600...
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H A Dsha1-parisc.pl2 # Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved.
17 # SHA1 block procedure for PA-RISC.
21 # On PA-7100LC performance is >30% better than gcc 3.2 generated code
23 # compiler on PA-8600 it's almost 60% faster in 64-bit build and just
24 # few percent faster in 32-bit one (this for aligned input, data for
27 # Special thanks to polarhome.com for providing HP-UX account.
56 $FRAME=14*$SIZE_T+$FRAME_MARKER;# 14 saved regs + frame marker
71 sub BODY_00_19 {
102 sub BODY_20_39 {
136 sub BODY_40_59 {
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H A Dsha1-x86_64.pl2 # Copyright 2006-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # It was brought to my attention that on EM64T compiler-generated code
20 # was far behind 32-bit assembler implementation. This is unlike on
21 # Opteron where compiler-generated code was only 15% behind 32-bit
23 # There was suggestion to mechanically translate 32-bit code, but I
25 # capacity to fully utilize SHA-1 parallelism. Therefore this fresh
26 # implementation:-) However! While 64-bit code does perform better
27 # on Opteron, I failed to beat 32-bit assembler on EM64T core. Well,
28 # x86_64 does offer larger *addressable* bank, but out-of-order core
30 # core must have managed to run-time optimize even 32-bit code just as
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
74 unsigned getID() const { return MC->getID(); } in getID()
76 /// begin/end - Return all of the registers in this class.
78 iterator begin() const { return MC->begin(); } in begin()
79 iterator end() const { return MC->end(); } in end()
82 unsigned getNumRegs() const { return MC->getNumRegs(); } in getNumRegs()
90 return MC->getRegister(i); in getRegister()
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/freebsd/crypto/openssl/crypto/bn/asm/
H A Dsparcv9a-mont.pl2 # Copyright 2005-2021 The OpenSSL Project Authors. All Rights Reserved.
24 # binary compatibility. Well yes, it does exclude SPARC64 prior-V(!)
29 # integer-only pure SPARCv9 module to "fall down" to.
31 # USI&II cores currently exhibit uniform 2x improvement [over pre-
37 # out-of-order execution, which *might* mean that integer multiplier
39 # additional note, SPARC64 V implements FP Multiply-Add instruction,
41 # as Fujitsu SPARC64 V goes, talk to the author:-)
43 # The implementation implies following "non-natural" limitations on
45 # - num may not be less than 4;
46 # - num has to be even;
[all …]
H A Dparisc-mont.pl2 # Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved.
17 # On PA-7100LC this module performs ~90-50% better, less for longer
18 # keys, than code generated by gcc 3.2 for PA-RISC 1.1. Latter means
19 # that compiler utilized xmpyu instruction to perform 32x32=64-bit
24 # toward 4 times 16x16=32-bit multiplications [plus complementary
27 # for PA-RISC 1.1, but the "baseline" is far from optimal. The actual
28 # improvement coefficient was never collected on PA-7100LC, or any
30 # vendor compiler. But to give you a taste, PA-RISC 1.1 code path
32 # of ~5x on PA-8600.
34 # On PA-RISC 2.0 it has to compete with pa-risc2[W].s, which is
[all …]
H A Dx86-mont.pl2 # Copyright 2005-2020 The OpenSSL Project Authors. All Rights Reserved.
20 # First of all non-SSE2 path should be implemented (yes, for now it
21 # performs Montgomery multiplication/convolution only on SSE2-capable
23 # can be unrolled and modulo-scheduled to improve ILP and possibly
24 # moved to 128-bit XMM register bank (though it would require input
28 # 110%(!), rsa1024 one - by 70% and rsa4096 - by 20%:-)
32 # Modulo-scheduling SSE2 loops results in further 15-20% improvement.
33 # Integer-only code [being equipped with dedicated squaring procedure]
45 for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
66 $frame=32; # size of above frame rounded up to 16n
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_common_interceptors_vfork_i386.inc.S10 // Store return address in the spill area and tear down the stack frame.
11 sub $12, %esp
21 add $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
24 // Restore the stack frame.
28 // (%esp) call frame (arg0) for __*_handle_vfork
29 sub $16, %esp
38 add $_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.L1$pb), %ebx
/freebsd/sys/arm/arm/
H A Dexception.S3 /*-
4 * Copyright (c) 1994-1997 Mark Brinicombe.
77 * PUSHFRAME - macro to push a trap frame on the stack in the current mode
81 sub sp, sp, #4; /* Align the stack */ \
82 str lr, [sp, #-4]!; /* Push the return address */ \
83 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
84 stmia sp, {r0-r12}; /* Push the user mode registers */ \
86 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
89 str r0, [sp, #-4]!;
92 * PULLFRAME - macro to pull a trap frame from the stack in the current mode
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/freebsd/crypto/openssl/crypto/
H A Dsparccpuid.S1 ! Copyright 2005-2016 The OpenSSL Project Authors. All Rights Reserved.
9 # define ABI64 /* They've said -xarch=v9 at command line */
11 # define ABI64 /* They've said -m64 at command line */
17 # define FRAME -192 macro
20 # define FRAME -96 macro
33 save %sp,FRAME,%sp
43 mov .zero-(.-4),%o0
51 ! to determine if the CPU the code is executing on is V8- or
52 ! V9-compliant, as V9 returns a distinct value of 0x99,
148 save %sp,FRAME,%sp
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/freebsd/sys/cddl/dev/fbt/aarch64/
H A Dfbt_isa.c21 * Portions Copyright 2006-2008 John Birrell jb@freebsd.org
42 fbt_invop(uintptr_t addr, struct trapframe *frame, uintptr_t rval) in fbt_invop() argument
50 for (; fbt != NULL; fbt = fbt->fbtp_hashnext) { in fbt_invop()
51 if ((uintptr_t)fbt->fbtp_patchpoint != addr) in fbt_invop()
54 cpu->cpu_dtrace_caller = addr; in fbt_invop()
56 if (fbt->fbtp_roffset == 0) { in fbt_invop()
57 dtrace_probe(fbt->fbtp_id, frame->tf_x[0], in fbt_invop()
58 frame->tf_x[1], frame->tf_x[2], in fbt_invop()
59 frame->tf_x[3], frame->tf_x[4]); in fbt_invop()
61 dtrace_probe(fbt->fbtp_id, fbt->fbtp_roffset, rval, in fbt_invop()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td1 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 /// CCIfAlign - Match of the original alignment of the arg
15 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
68 //===----------------------------------------------------------------------===//
70 //===----------------------------------------------------------------------===//
82 // CPRCs may be allocated to co-processor registers or the stack - they
[all …]
/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghash-parisc.pl2 # Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # The module implements "4-bit" GCM GHASH function and underlying
20 # single multiplication operation in GF(2^128). "4-bit" means that it
21 # uses 256 bytes per-key table [+128 bytes shared table]. On PA-7100LC
23 # fast as code generated by gcc 3.2. PA-RISC 2.0 loop is scheduled for
24 # 8 cycles, but measured performance on PA-8600 system is ~9 cycles per
25 # processed byte. This is ~2.2x faster than 64-bit code generated by
26 # vendor compiler (which used to be very hard to beat:-).
28 # Special thanks to polarhome.com for providing HP-UX account.
59 $FRAME=10*$SIZE_T+$FRAME_MARKER;# NREGS saved regs + frame marker
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiFrameLowering.cpp1 //===-- LanaiFrameLowering.cpp - Lanai Frame Information ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
26 // Determines the size of the frame and maximum call frame size.
36 LRI->hasStackRealignment(MF) ? MFI.getMaxAlign() : getStackAlign(); in determineFrameLayout()
38 // Get the maximum call frame size of all the calls. in determineFrameLayout()
46 // Update maximum call frame size. in determineFrameLayout()
49 // Include call frame size in total. in determineFrameLayout()
53 // Make sure the frame is aligned. in determineFrameLayout()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
38 const AVRMachineFunctionInfo *AFI = MF->getInfo<AVRMachineFunctionInfo>(); in getCalleeSavedRegs()
39 const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>(); in getCalleeSavedRegs()
41 return AFI->isInterruptOrSignalHandler() ? CSR_InterruptsTiny_SaveList in getCalleeSavedRegs()
44 return AFI->isInterruptOrSignalHandler() ? CSR_Interrupts_SaveList in getCalleeSavedRegs()
72 // Reserve 8-bit registers R2~R15, Rtmp(R16) and Zero(R17). in getReservedRegs()
75 // Reserve 16-bit registers R3R2~R18R17. in getReservedRegs()
[all …]
/freebsd/crypto/openssl/crypto/perlasm/
H A Dx86_64-xlate.pl2 # Copyright 2005-2020 The OpenSSL Project Authors. All Rights Reserved.
14 # Unix ABI to Windows one [see cross-reference "card" at the end of
23 # enough to provide for dual-ABI OpenSSL modules development...
29 # - can't use multiple ops per line;
31 # Dual-ABI styling rules.
33 # 1. Adhere to Unix register and stack layout [see cross-reference
36 # stack frame allocation. If volatile storage is actually required
41 # ".type name,@abi-omnipotent" instead.
44 # larger than 6, then you *have to* write "abi-omnipotent" code,
48 # 6. Don't use [or hand-code with .byte] "rep ret." "ret" mnemonic is
[all …]
/freebsd/crypto/openssl/crypto/camellia/asm/
H A Dcmll-x86.pl2 # Copyright 2008-2020 The OpenSSL Project Authors. All Rights Reserved.
25 # -evp camellia-128-ecb 21.5 22.8 27.0 28.9
29 # camellia-128-cbc 17.3 21.1 23.9 25.9
31 # 128-bit key setup 196 280 256 240 cycles/key
36 # compiler generated position-independent code, PIC, and non-PIC
38 # is position-independent, i.e. suitable for a shared library or PIE.
40 # are so close with non-PIC results, they have an extra register to
41 # spare. CBC results are better than ECB ones thanks to "zero-copy"
42 # private _x86_* interface, and are ~30-40% better than with compiler
43 # generated cmll_cbc.o, and reach ~80-90% of x86_64 performance on
[all …]

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