1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
38   const AVRMachineFunctionInfo *AFI = MF->getInfo<AVRMachineFunctionInfo>();  in getCalleeSavedRegs()
39   const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();  in getCalleeSavedRegs()
41     return AFI->isInterruptOrSignalHandler() ? CSR_InterruptsTiny_SaveList  in getCalleeSavedRegs()
44     return AFI->isInterruptOrSignalHandler() ? CSR_Interrupts_SaveList  in getCalleeSavedRegs()
72     // Reserve 8-bit registers R2~R15, Rtmp(R16) and Zero(R17).  in getReservedRegs()
75     // Reserve 16-bit registers R3R2~R18R17.  in getReservedRegs()
80   // We tenatively reserve the frame pointer register r29:r28 because the  in getReservedRegs()
87   //       but didn't end up needing a frame pointer. In these, we can  in getReservedRegs()
100   if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {  in getLargestLegalSuperClass()
104   if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {  in getLargestLegalSuperClass()
111 /// Fold a frame offset shared between two add instructions into a single one.
117   // Don't bother trying if the next instruction is not an add or a sub.  in foldFrameOffset()
131     Offset += -MI.getOperand(2).getImm();  in foldFrameOffset()
153   const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();  in eliminateFrameIndex()
155   const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();  in eliminateFrameIndex()
161   Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;  in eliminateFrameIndex()
166   // instruction. We have only two-address instructions, thus we need to  in eliminateFrameIndex()
170     assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");  in eliminateFrameIndex()
172     // Copy the frame pointer.  in eliminateFrameIndex()
192     // Generally, to load a frame address two add instructions are emitted that  in eliminateFrameIndex()
217       Offset = -Offset;  in eliminateFrameIndex()
225     New->getOperand(3).setIsDead();  in eliminateFrameIndex()
236   // adjusting the frame pointer.  in eliminateFrameIndex()
239   // If the offset is too big we have to adjust and restore the frame pointer  in eliminateFrameIndex()
241   //: TODO: consider using only one adiw/sbiw chain for more than one frame  in eliminateFrameIndex()
245     int AddOffset = Offset - MaxOffset;  in eliminateFrameIndex()
248     if ((Offset - MaxOffset) > 63 || !STI.hasADDSUBIW()) {  in eliminateFrameIndex()
251       AddOffset = -AddOffset;  in eliminateFrameIndex()
254     // It is possible that the spiller places this frame instruction in between  in eliminateFrameIndex()
256     // compare instruction because of the add/sub pairs. Conservatively save and  in eliminateFrameIndex()
257     // restore SREG before and after each add/sub pair.  in eliminateFrameIndex()
264     New->getOperand(3).setIsDead();  in eliminateFrameIndex()
275         .addImm(Offset - MaxOffset);  in eliminateFrameIndex()
288   if (TFI->hasFP(MF)) {  in getFrameRegister()
299   // FIXME: Currently we're using avr-gcc as reference, so we restrict  in getPointerRegClass()
300   // ptrs to Y and Z regs. Though avr-gcc has buggy implementation  in getPointerRegClass()
301   // of memory constraint, so we can fix it and bit avr-gcc here ;-)  in getPointerRegClass()
307   assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");  in splitReg()
317   if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {  in shouldCoalesce()