Lines Matching +full:sub +full:- +full:frame
1 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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9 //===----------------------------------------------------------------------===//
11 /// CCIfAlign - Match of the original alignment of the arg
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17 //===----------------------------------------------------------------------===//
68 //===----------------------------------------------------------------------===//
70 //===----------------------------------------------------------------------===//
82 // CPRCs may be allocated to co-processor registers or the stack - they
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
125 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
134 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
155 //===----------------------------------------------------------------------===//
157 //===----------------------------------------------------------------------===//
202 //===----------------------------------------------------------------------===//
203 // ARM AAPCS-VFP (EABI) Calling Convention
205 //===----------------------------------------------------------------------===//
263 //===----------------------------------------------------------------------===//
264 // Callee-saved register lists.
265 //===----------------------------------------------------------------------===//
279 def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>;
282 def CSR_AAPCS_SwiftTail : CalleeSavedRegs<(sub CSR_AAPCS, R10)>;
284 // The order of callee-saved registers needs to match the order we actually push
286 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
297 def CSR_ATPCS_SplitPush_SwiftError : CalleeSavedRegs<(sub CSR_ATPCS_SplitPush,
301 def CSR_ATPCS_SplitPush_SwiftTail : CalleeSavedRegs<(sub CSR_ATPCS_SplitPush,
304 // When enforcing an AAPCS compliant frame chain, R11 is used as the frame
306 // This AAPCS alternative makes sure the frame index slots match the push
315 // be partially modelled by treating R0 as a callee-saved register
321 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
322 // Also save R7-R4 first to match the stack frame fixed spill areas.
323 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
326 def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>;
329 def CSR_iOS_SwiftTail : CalleeSavedRegs<(sub CSR_iOS, R10)>;
332 (sub CSR_AAPCS_ThisReturn, R9))>;
335 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
347 def CSR_iOS_CXX_TLS_ViaCopy : CalleeSavedRegs<(sub CSR_iOS_CXX_TLS,
351 // exception-handlers of various kinds. It makes us use a different return
356 // user-space. We mark LR to be saved anyway, since this is what the ARM backend
361 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
363 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
364 // current frame lowering expects to encounter it while processing callee-saved