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Searched +full:sparx5 +full:- +full:cpu +full:- +full:syscon (Results 1 – 10 of 10) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/microchip/
H A Dmicrochip,sparx5-cpu-syscon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,sparx5-cpu-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 CPU Syscon
10 - Lars Povlsen <lars.povlsen@microchip.com>
15 - const: microchip,sparx5-cpu-syscon
16 - const: syscon
17 - const: simple-mfd
22 mux-controller:
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/linux/Documentation/devicetree/bindings/reset/
H A Dmicrochip,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Switch Reset Controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
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/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
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/linux/drivers/power/reset/
H A Docelot-reset.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
12 #include <linux/mfd/syscon.h>
19 const char *syscon; member
48 u32 if_si_owner_bit = ctx->props->if_si_owner_bit; in ocelot_restart_handle()
51 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in ocelot_restart_handle()
52 ctx->props->vcore_protect, 0); in ocelot_restart_handle()
56 regmap_update_bits(ctx->cpu_ctrl, in ocelot_restart_handle()
63 writel(SOFT_CHIP_RST, ctx->base); in ocelot_restart_handle()
72 struct device *dev = &pdev->dev; in ocelot_reset_probe()
75 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in ocelot_reset_probe()
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/linux/drivers/mmc/host/
H A Dsdhci-of-sparx5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/mmc/host/sdhci-of-sparx5.c
5 * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
16 #include <linux/mfd/syscon.h>
17 #include <linux/dma-mapping.h>
20 #include "sdhci-pltfm.h"
46 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
64 mmc_hostname(host->mmc), len, &addr); in sdhci_sparx5_adma_write_desc()
66 offset = addr & (SZ_128M - 1); in sdhci_sparx5_adma_write_desc()
67 tmplen = SZ_128M - offset; in sdhci_sparx5_adma_write_desc()
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/linux/drivers/reset/
H A Dreset-microchip-sparx5.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch Reset driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 #include <linux/mfd/syscon.h>
15 #include <linux/reset-controller.h>
42 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in sparx5_switch_reset()
43 ctx->props->protect_bit, ctx->props->protect_bit); in sparx5_switch_reset()
46 regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, in sparx5_switch_reset()
47 ctx->props->reset_bit); in sparx5_switch_reset()
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/linux/drivers/spi/
H A Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
15 #include <linux/mfd/syscon.h>
24 #include "spi-dw.h"
52 struct regmap *syscon; member
53 void __iomem *spi_mst; /* Not sparx5 */
61 * bit: |---3-------2-------1-------0
79 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_mscc_set_cs()
81 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_mscc_set_cs()
90 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); in dw_spi_mscc_set_cs()
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/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
22 #include <linux/mfd/syscon.h>
33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
217 static int sparx5_create_targets(struct sparx5 *sparx5) in sparx5_create_targets() argument
228 if (idx == iomap->range) { in sparx5_create_targets()
234 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
237 dev_err(sparx5->dev, "Invalid resource\n"); in sparx5_create_targets()
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/linux/arch/arm/boot/dts/microchip/
H A Dlan966x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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