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/linux/Documentation/devicetree/bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
16 Until these IP blocks (or IP integration) support version
17 auto-discovery, the maintainers of these IP blocks intend to increment
19 interface to these IP blocks changes, or when the functionality of the
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/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
19 numbers can be found here -
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
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/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: serial.yaml#
20 - enum:
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/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive Core Local Interruptor
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
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/linux/arch/riscv/crypto/
H A Daes-riscv64-zvkned.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
15 // Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com>
16 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
41 // The generated code of this file depends on the following RISC-V extensions:
42 // - RV64I
43 // - RISC-V Vector ('V') with VLEN >= 128
44 // - RISC-V Vector AES block cipher extension ('Zvkned')
51 #include "aes-macros.S"
88 // t0 is the remaining length in 32-bit words. It's a multiple of 4.
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H A Daes-riscv64-zvkned-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
14 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128
42 // - RISC-V Vector AES block cipher extension ('Zvkned')
43 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
50 #include "aes-macros.S"
63 // LEN32 = number of blocks, rounded up, in 32-bit words.
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H A Daes-macros.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
15 // Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com>
16 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
41 // This file contains macros that are shared by the other aes-*.S files. The
42 // generated code of these macros depends on the following RISC-V extensions:
43 // - RV64I
44 // - RISC-V Vector ('V') with VLEN >= 128
45 // - RISC-V Vector AES block cipher extension ('Zvkned')
49 // - If AES-128, loads round keys into v1-v11 and jumps to \label128.
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H A Daes-riscv64-zvkned-zvbb-zvkg.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
14 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128 && VLEN < 2048
42 // - RISC-V Vector AES block cipher extension ('Zvkned')
43 // - RISC-V Vector Bit-manipulation extension ('Zvbb')
44 // - RISC-V Vector GCM/GMAC extension ('Zvkg')
51 #include "aes-macros.S"
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H A Daes-riscv64-glue.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AES using the RISC-V vector crypto extensions. Includes the bare block
4 * cipher and the ECB, CBC, CBC-CTS, CTR, and XTS modes.
9 * Copyright (C) 2023 SiFive, Inc.
10 * Author: Jerry Shih <jerry.shih@sifive.com>
69 * - zvkned's key expansion instructions don't support AES-192. in riscv64_aes_setkey()
70 * So, non-zvkned fallback code would be needed anyway. in riscv64_aes_setkey()
72 * - Users of AES in Linux usually don't change keys frequently. in riscv64_aes_setkey()
73 * So, key expansion isn't performance-critical. in riscv64_aes_setkey()
75 * - For single-block AES exposed as a "cipher" algorithm, it's in riscv64_aes_setkey()
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/linux/drivers/tty/serial/
H A Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
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/linux/lib/crypto/riscv/
H A Dchacha-riscv64-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
14 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128
42 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
87 vror.vi \d0, \d0, 32 - 16
88 vror.vi \d1, \d1, 32 - 16
89 vror.vi \d2, \d2, 32 - 16
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H A Dsha512-riscv64-zvknhb-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
15 // Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com>
40 // The generated code of this file depends on the following RISC-V extensions:
41 // - RV64I
42 // - RISC-V Vector ('V') with VLEN >= 128
43 // - RISC-V Vector SHA-2 Secure Hash extension ('Zvknhb')
44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
70 // Do 4 rounds of SHA-512. w0 contains the current 4 message schedule words.
73 // computes 4 more message schedule words. w1-w3 contain the next 3 groups of 4
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H A Dsha256-riscv64-zvknha_or_zvknhb-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
15 // Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com>
40 // The generated code of this file depends on the following RISC-V extensions:
41 // - RV64I
42 // - RISC-V Vector ('V') with VLEN >= 128
43 // - RISC-V Vector SHA-2 Secure Hash extension ('Zvknha' or 'Zvknhb')
44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
85 // Do 4 rounds of SHA-256. w0 contains the current 4 message schedule words.
88 // computes 4 more message schedule words. w1-w3 contain the next 3 groups of 4
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/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
69 This enables support for SPI-NAND mode on the Airoha NAND
71 is implemented as a SPI-MEM controller.
107 This enables master mode support for the SPISG (SPI scatter-gather
119 to a single device like spi-nor (nvram), input device controller
178 supports spi-mem interface.
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/linux/drivers/gpio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
50 this symbol, but new drivers should use the generic gpio-regmap
60 non-sleeping contexts. They can make bitbanged serial protocols
81 numberspace-based functionalities of the sysfs interface.
137 Enables support for the idio-16 library functions. The idio-16 library
139 ACCES IDIO-16 family such as the 104-IDIO-16 and the PCI-IDIO-16.
141 If built as a module its name will be gpio-idio-16.
147 tristate "GPIO driver for 74xx-ICs with MMIO access"
151 Say yes here to support GPIO functionality for 74xx-compatible ICs
166 If driver is built as a module it will be called gpio-altera.
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