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/titanic_52/usr/src/uts/common/sys/sata/adapters/nv_sata/
H A Dnv_sgpio.h36 * SGPIO Command Timeout (2000ms, in nsecs)
41 * SGPIO Configuration Space Offsets
48 * SGPIO Command/Status Register
80 /* SGPIO Status field - read-only */
86 /* SGPIO Status field values */
93 * SGPIO Control Block
112 uint32_t sgpio0_tr; /* SGPIO 0 Transmit Register */
113 uint32_t sgpio1_tr; /* SGPIO 1 Transmit Register */
120 * implementation of SGPIO and therefore not defined in SFF8485.
149 * SGPIO Configuratio
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H A Dnv_sata.h36 * SGPIO Support
37 * Enable SGPIO support only on x86/x64, because it is implemented using
113 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */
114 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
115 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */
244 int nvs_cbp; /* SGPIO Control Block Pointer */
/titanic_52/usr/src/uts/common/io/sata/adapters/nv_sata/
H A Dnv_sata.c388 * When a MCP55/IO55 parts supports SGPIO, there is a single CBP (SGPIO
393 * driver state (called the 'common' area here) associated with each SGPIO
403 * area associated with that SGPIO CBP value, rather than initialize it
756 * initialize SGPIO in nv_attach()
951 * release SGPIO resources in nv_detach()
1075 * SGPIO (as per NVIDIA docs), this code will as well. in nv_ioctl()
1129 * SGPIO (as per NVIDIA docs), this code will as well. in nv_ioctl()
1180 * According to documentation, NVIDIA SGPIO is supposed to in nv_ioctl()
6443 * NVIDIA specific SGPIO LE
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/titanic_52/usr/src/uts/common/sys/sata/adapters/ahci/
H A Dahcireg.h111 #define AHCI_HBA_EM_CTL_SUPP_SGPIO (0x1 << 19) /* SGPIO EM Messages */
/titanic_52/usr/src/uts/common/io/scsi/adapters/mpt_sas/
H A Dmptsas.c16787 * Functions for SGPIO LED support
/titanic_52/usr/src/data/hwdata/
H A Dpci.ids22435 a02a ThunderX SGPIO (Serial GPIO controller for SATA disk lights)
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