1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ 2724ba675SRob Herring// Copyright (C) 2021 YADRO 3724ba675SRob Herring/dts-v1/; 4724ba675SRob Herring 5724ba675SRob Herring#include "aspeed-bmc-vegman.dtsi" 6724ba675SRob Herring 7724ba675SRob Herring/ { 8724ba675SRob Herring model = "YADRO VEGMAN Sx20 BMC"; 9724ba675SRob Herring compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500"; 10724ba675SRob Herring}; 11724ba675SRob Herring 12724ba675SRob Herring&gpio { 13724ba675SRob Herring status = "okay"; 14724ba675SRob Herring gpio-line-names = 15724ba675SRob Herring /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", 16724ba675SRob Herring /*B0-B7*/ "","","","","","","","", 17724ba675SRob Herring /*C0-C7*/ "","","","","","","","", 18724ba675SRob Herring /*D0-D7*/ "","","","","","","","", 19724ba675SRob Herring /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", 20724ba675SRob Herring /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","", 21724ba675SRob Herring /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", 22724ba675SRob Herring /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", 23724ba675SRob Herring /*I0-I7*/ "","","","","","","","", 24724ba675SRob Herring /*J0-J7*/ "","","","","","","","", 25724ba675SRob Herring /*K0-K7*/ "","","","","","","","", 26724ba675SRob Herring /*L0-L7*/ "","","","","","","","", 27724ba675SRob Herring /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","", 28724ba675SRob Herring /*N0-N7*/ "","","","","","","","", 29724ba675SRob Herring /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", 30724ba675SRob Herring /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","", 31724ba675SRob Herring /*Q0-Q7*/ "","","","","","","","", 32724ba675SRob Herring /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", 33724ba675SRob Herring /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", 34724ba675SRob Herring /*T0-T7*/ "","","","","","","","", 35724ba675SRob Herring /*U0-U7*/ "","","","","","","","", 36724ba675SRob Herring /*V0-V7*/ "","","","","","","","", 37724ba675SRob Herring /*W0-W7*/ "","","","","","","","", 38724ba675SRob Herring /*X0-X7*/ "","","","","","","","", 39724ba675SRob Herring /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", 40724ba675SRob Herring /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", 41724ba675SRob Herring /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", 42724ba675SRob Herring /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", 43724ba675SRob Herring /*AC0-AC7*/ "","","","","","","",""; 44724ba675SRob Herring}; 45724ba675SRob Herring 46724ba675SRob Herring&sgpio { 47724ba675SRob Herring ngpios = <80>; 48724ba675SRob Herring bus-frequency = <2000000>; 49724ba675SRob Herring status = "okay"; 50724ba675SRob Herring /* SGPIO lines. even: input, odd: output */ 51724ba675SRob Herring gpio-line-names = 52724ba675SRob Herring /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", 53724ba675SRob Herring /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", 54724ba675SRob Herring /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", 55724ba675SRob Herring /*D0-D7*/ "","","","","","","","","","","","","","","","", 56724ba675SRob Herring /*E0-E7*/ "","","","","","","","","","","","","","","","", 57724ba675SRob Herring /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", 58724ba675SRob Herring /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", 59724ba675SRob Herring /*H0-H7*/ "","","","","","","","","","","","","","","","", 60724ba675SRob Herring /*I0-I7*/ "","","","","","","","","","","","","","","","", 61724ba675SRob Herring /*J0-J7*/ "","","","","","","","","","","","","","","",""; 62724ba675SRob Herring}; 63724ba675SRob Herring 64724ba675SRob Herring&i2c11 { 65724ba675SRob Herring /* SMB_BMC_MGMT_LVC3 */ 66724ba675SRob Herring gpio@21 { 67724ba675SRob Herring compatible = "nxp,pcal9535"; 68724ba675SRob Herring reg = <0x21>; 69724ba675SRob Herring gpio-controller; 70724ba675SRob Herring #gpio-cells = <2>; 71724ba675SRob Herring gpio-line-names = 72724ba675SRob Herring /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT", 73724ba675SRob Herring /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT"; 74724ba675SRob Herring }; 75724ba675SRob Herring gpio@27 { 76724ba675SRob Herring compatible = "nxp,pca9698"; 77724ba675SRob Herring reg = <0x27>; 78724ba675SRob Herring gpio-controller; 79724ba675SRob Herring #gpio-cells = <2>; 80724ba675SRob Herring gpio-line-names = 81724ba675SRob Herring /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", 82724ba675SRob Herring /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", 83724ba675SRob Herring /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", 84724ba675SRob Herring /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", 85724ba675SRob Herring /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", ""; 86724ba675SRob Herring }; 87724ba675SRob Herring}; 88724ba675SRob Herring 89724ba675SRob Herring&i2c13 { 90724ba675SRob Herring /* SMB_PCIE2_STBY_LVC3 */ 91*4b46d86cSGeert Uytterhoeven i2c-mux@71 { 92*4b46d86cSGeert Uytterhoeven compatible = "nxp,pca9543"; 93*4b46d86cSGeert Uytterhoeven reg = <0x71>; 94724ba675SRob Herring #address-cells = <1>; 95724ba675SRob Herring #size-cells = <0>; 96724ba675SRob Herring i2c-mux-idle-disconnect; 97724ba675SRob Herring }; 98*4b46d86cSGeert Uytterhoeven i2c-mux@73 { 99*4b46d86cSGeert Uytterhoeven compatible = "nxp,pca9545"; 100*4b46d86cSGeert Uytterhoeven reg = <0x73>; 101724ba675SRob Herring #address-cells = <1>; 102724ba675SRob Herring #size-cells = <0>; 103724ba675SRob Herring i2c-mux-idle-disconnect; 104724ba675SRob Herring }; 105724ba675SRob Herring}; 106724ba675SRob Herring 107724ba675SRob Herring&i2c2 { 108724ba675SRob Herring /* SMB_PCIE_STBY_LVC3 */ 109*4b46d86cSGeert Uytterhoeven i2c-mux@71 { 110724ba675SRob Herring compatible = "nxp,pca9545"; 111724ba675SRob Herring reg = <0x71>; 112724ba675SRob Herring #address-cells = <1>; 113724ba675SRob Herring #size-cells = <0>; 114724ba675SRob Herring i2c-mux-idle-disconnect; 115724ba675SRob Herring }; 116724ba675SRob Herring}; 117724ba675SRob Herring 118724ba675SRob Herring&pwm_tacho { 119724ba675SRob Herring status = "okay"; 120724ba675SRob Herring pinctrl-names = "default"; 121724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default 122724ba675SRob Herring &pinctrl_pwm2_default &pinctrl_pwm3_default 123724ba675SRob Herring &pinctrl_pwm4_default &pinctrl_pwm5_default 124724ba675SRob Herring &pinctrl_pwm6_default>; 125724ba675SRob Herring 126724ba675SRob Herring fan@0 { 127724ba675SRob Herring reg = <0x00>; 128724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x00>; 129724ba675SRob Herring }; 130724ba675SRob Herring fan@1 { 131724ba675SRob Herring reg = <0x01>; 132724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x01>; 133724ba675SRob Herring }; 134724ba675SRob Herring fan@2 { 135724ba675SRob Herring reg = <0x02>; 136724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x02>; 137724ba675SRob Herring }; 138724ba675SRob Herring fan@3 { 139724ba675SRob Herring reg = <0x03>; 140724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x03>; 141724ba675SRob Herring }; 142724ba675SRob Herring fan@4 { 143724ba675SRob Herring reg = <0x04>; 144724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x04>; 145724ba675SRob Herring }; 146724ba675SRob Herring fan@5 { 147724ba675SRob Herring reg = <0x05>; 148724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x05>; 149724ba675SRob Herring }; 150724ba675SRob Herring fan@6 { 151724ba675SRob Herring reg = <0x06>; 152724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x06>; 153724ba675SRob Herring }; 154724ba675SRob Herring}; 155