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/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-poeg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be
14 disabled by using the port output enabling function for the GPT (POEG).
17 * Output-disable request from the GPT.
21 are controlled by the GPT module.
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/linux/Documentation/devicetree/bindings/pwm/
H A Drenesas,rzg2l-gpt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L General PWM Timer (GPT)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
16 * Up-counting or down-counting (saw waves) or up/down-counting
36 short-circuits between output pins.
42 pwm0 - GPT32E0.GTIOC0A channel
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/linux/drivers/pwm/
H A Dpwm-rzg2l-gpt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L General PWM Timer (GPT) driver
8 …* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?lang…
11 * - Counter must be stopped before modifying Mode and Prescaler.
12 * - When PWM is disabled, the output is driven to inactive.
13 * - While the hardware supports both polarities, the driver (for now)
15 * - General PWM Timer (GPT) has 8 HW channels for PWM operations and
17 * - Each IO is modelled as an independent PWM channel.
18 * - When both channels are used, disabling the channel on one stops the
20 * - When both channels are used, the period of both IOs in the HW channel
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g044l2-smarc.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
31 * To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the
38 #include "rzg2l-smarc-som.dtsi"
39 #include "rzg2l-smarc-pinfunction.dtsi"
40 #include "rz-smarc-common.dtsi"
41 #include "rzg2l-smarc.dtsi"
45 compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
H A Dr9a07g054l2-smarc.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
30 * To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the
37 #include "rzg2l-smarc-som.dtsi"
38 #include "rzg2l-smarc-pinfunction.dtsi"
39 #include "rz-smarc-common.dtsi"
40 #include "rzg2l-smarc.dtsi"
44 compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054";
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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H A Drzg2l-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
17 osc1: cec-clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12000000>;
23 hdmi-out {
24 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
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H A Drzg2l-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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