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Searched +full:rxclk +full:- +full:pins (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
16 Available mpp pins/groups and functions:
22 name pins functions
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
[all …]
H A Dmarvell,armada-375-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
45 mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
71 mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
19 name pins functions
32 mpp11 11 gpio, ge0(rxclk), lcd(d11)
44 mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
61 mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
[all …]
H A Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
20 mpp4 4 gpio, vdd(cpu-pd)
37 mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
51 mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
99 one example of a gpio usage on the board D-Link DNS-327L
H A Dmarvell,armada-38x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
35 mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt)
55 mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
H A Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
12 Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
[all …]
H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
56 mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk)
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
18 -------
23 - a set of core clocks
24 - a set of gateable clocks
28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30 - The second cell identifies the particular core clock or gateable
34 - Core clocks
35 - 0 0 APLL
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7100-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
21 stdout-path = "serial0:115200n8";
25 timebase-frequency = <6250000>;
34 compatible = "gpio-leds";
36 led-ack {
40 linux,default-trigger = "heartbeat";
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-xp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
12 * both have 67 MPP pins (more GPIOs and address lines for the memory
26 #include "pinctrl-mvebu.h"
89 MPP_VAR_FUNCTION(0x1, "ge0", "rxclk", V_MV78230_PLUS),
158 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS),
189 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
235 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
243 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
[all …]
/linux/drivers/tty/
H A Dsynclink_gt.c1 // SPDX-License-Identifier: GPL-1.0+
28 * DBGINFO information - most verbose output
146 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
496 printk("%s %s data:\n",info->device_name, label); in trace_block()
511 count -= linecount; in trace_block()
522 printk("tbuf_current=%d\n", info->tbuf_current); in dump_tbufs()
523 for (i=0 ; i < info->tbuf_count ; i++) { in dump_tbufs()
525 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); in dump_tbufs()
536 printk("rbuf_current=%d\n", info->rbuf_current); in dump_rbufs()
537 for (i=0 ; i < info->rbuf_count ; i++) { in dump_rbufs()
[all …]
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun6i-a31.c6 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 #include "pinctrl-sunxi.h"
189 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
950 /* Undocumented mux function - see above */
952 /* 2 extra pins for A31 */
964 .pins = sun6i_a31_pins,
973 (unsigned long)of_device_get_match_data(&pdev->dev); in sun6i_a31_pinctrl_probe()
982 .compatible = "allwinner,sun6i-a31-pinctrl",
986 .compatible = "allwinner,sun6i-a31s-pinctrl",
995 .name = "sun6i-a31-pinctrl",