reset\-gpio (full) in projects: linux - OpenGrok search results

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Searched +full:reset +full:- +full:gpio (Results 1 – 25 of 69) sorted by relevance

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/illumos-gate/usr/src/uts/sun4u/io/
H A D	pmugpio.c	`37 * The pmugpio driver supports ALOM GPIO bits for resetSC and 41 * Minneapolis/Boston Controller (MBC) FPGA GPIO and Seattle CPLD 42 * GPIO. 46 PMUGPIO_MBC, /* Boston MBC FPGA GPIO - 8-bit / 47 PMUGPIO_CPLD, / Seattle CPLD GPIO - 8-bit / 48 PMUGPIO_OTHER / Chalupa - 8-bit / 52 FWARC 2005/686: gpio device compatible property 54 #define PMUGPIO_DEVICE_TYPE "gpio-device-type" 57 * CPLD GPIO Register defines. 59 #define CPLD_RESET_SC 0x01 /* Reset SC */ [all …]`
H A D	gpio_87317.c	111 nulldev, /* reset / 123 "gpio driver", 184 result = (void )softc->gp_dip; in gpio_getinfo() 218 softc->gp_dip = dip; in gpio_attach() 219 softc->gp_state = 0; in gpio_attach() 220 mutex_init(&softc->gp_mutex, NULL, MUTEX_DRIVER, NULL); in gpio_attach() 222 / Map in the gpio device registers. / in gpio_attach() 227 if (ddi_regs_map_setup(dip, 0, (caddr_t )&softc->gp_regs, 0, 0, in gpio_attach() 228 &dev_attr, &softc->gp_handle) != DDI_SUCCESS) in gpio_attach() 230 DBG(dip, "attach: regs=0x%p", (uintptr_t)softc->gp_regs, in gpio_attach() [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	misc_bits.h	69 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) //(NIG - Reset … 70 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) //(NIG - Reset … 71 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) //(NIG - Reset … 72 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) //(NIG - Reset … 73 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) //(NIG - Reset … 74 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) //(NIG - Reset … 75 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) //(NIG - Reset … 76 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) //(NIG - Reset … 77 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) //(NIG - Reset … 78 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_RSTB_HW (0x1<<16) //(NIG - Reset … [all …]
/illumos-gate/usr/src/uts/common/io/audio/drv/audiocmihd/
H A D	audiocmihd.c	`32 * Copyright (C) 4Front Technologies 1996-2011. 153 vol = (vol * ((1 << bits) - 1)) / 100; in mix_scale() 164 mutex_enter(&devc->low_mutex); in cmediahd_read_ac97() 172 mutex_exit(&devc->low_mutex); in cmediahd_read_ac97() 182 mutex_enter(&devc->low_mutex); in cmediahd_write_ac97() 190 mutex_exit(&devc->low_mutex); in cmediahd_write_ac97() 201 mutex_enter(&devc->low_mutex); 209 mutex_exit(&devc->low_mutex); 220 mutex_enter(&devc->low_mutex); 228 mutex_exit(&devc->low_mutex); [all …]`
/illumos-gate/usr/src/uts/common/io/axf/
H A D	axf_usbgem.c	4 * Copyright (c) 2004-2012 Masayuki Murayama. All rights reserved. 82 (((struct axf_dev )(dp)->private)->chip->type == CHIP_TYPE_AX88172) 85 (((struct axf_dev )(dp)->private)->chip->type == CHIP_TYPE_AX88772) 127 /* Planex UE2-100TX, Hawking UF200, TrendNet TU2-ET100 / 132 gpio bit2 has to be 0 and gpio bit0 has to be 1 137 "Planex UE2-100TX", /* tested / 142 "D-Link dube100", / XXX */ 172 "Buffalo LUA-U2-KTX", 177 "Sitecom LN-029 USB 2.0 10/100 Ethernet adapter", 182 "corega FEther USB2-TX", [all …]
H A D	ax88172reg.h	`121 /* GPIO register / 140 / Software reset register / 142 #define SWRST_IPRL 0x20 / internal phy reset control / 143 #define SWRST_BZ 0x10 / force Bulk In to return zero-length pkt / 144 #define SWRST_PRL 0x08 / external phy reset pin level / 145 #define SWRST_PRTE 0x04 / external phy tri-state enable / 146 #define SWRST_RT 0x02 / clear frame length error for Bulk-Out / 147 #define SWRST_RR 0x01 / clear frame length error for Bulk-In */`
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A D	lm_hw_access.c	56 #define INVALID_NIG_OFFSET ((u8_t)-1) 65 u8_t num_vnics = pdev->params.vnics_per_port; in lm_cmng_init() 67 …const u8_t port_id = PORT_ID(pdev); // TBD: E1H - cmng params are c… in lm_cmng_init() 69 … = 1 ; /* default MIN rate in case VNIC min rate is configured to zero- 100Mbps / in lm_cmng_init() 73 if(IS_MULTI_VNIC(pdev) && pdev->params.cmng_enable) in lm_cmng_init() 85 if (!GET_FLAGS(pdev->hw_info.mf_info.func_mf_cfg , FUNC_MF_CFG_FUNC_HIDE)) in lm_cmng_init() 87 if (pdev->hw_info.mf_info.min_bw[vnic] == 0) in lm_cmng_init() 93 input_data.vnic_min_rate[vnic] = pdev->hw_info.mf_info.min_bw[vnic]; in lm_cmng_init() 184 Initialize a NIG mirror entry to a given MAC address. Note - 199 lm_nig_mirror_entry_t* entry = &pdev->vars.nig_mirror.entries[offset]; in lm_initialize_nig_entry() [all …]
/illumos-gate/usr/src/uts/common/io/ib/adapters/hermon/
H A D	hermon_ioctl.c	53 * (DEBUG-only), and VTS interfaces) 165 if (instance == (minor_t)-1) { in hermon_ioctl() 251 mutex_enter(&state->hs_fw_flashlock); in hermon_ioctl_flash_read() 252 if ((state->hs_fw_flashdev != dev) \|\| in hermon_ioctl_flash_read() 253 (state->hs_fw_flashstarted == 0)) { in hermon_ioctl_flash_read() 254 mutex_exit(&state->hs_fw_flashlock); in hermon_ioctl_flash_read() 265 mutex_exit(&state->hs_fw_flashlock); in hermon_ioctl_flash_read() 276 mutex_exit(&state->hs_fw_flashlock); in hermon_ioctl_flash_read() 287 (state->hs_fw_device_sz >> state->hs_fw_log_sector_sz)) { in hermon_ioctl_flash_read() 288 mutex_exit(&state->hs_fw_flashlock); in hermon_ioctl_flash_read() [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A D	ecore_mcp_api.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 185 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 605 * @brief - returns the link params of the hw function 614 * @brief - return the link state of the hw function 623 * @brief - return the link capabilities of the hw function 637 * @param b_up - raise link if `true'. Reset link if `false'. 650 * @param p_mfw_ver - mfw version value 651 * @param p_running_bundle_id - image id in nvram; Optional. [all …]
/illumos-gate/usr/src/uts/common/io/audio/drv/audiols/
H A D	audiols.c	30 * Copyright (C) 4Front Technologies 1996-2009. 153 mutex_enter(&dev->low_mutex); in read_chan() 158 mutex_exit(&dev->low_mutex); in read_chan() 166 mutex_enter(&dev->low_mutex); in write_chan() 171 mutex_exit(&dev->low_mutex); in write_chan() 194 mutex_enter(&dev->low_mutex); in audigyls_read_ac97() 201 mutex_exit(&dev->low_mutex); in audigyls_read_ac97() 205 mutex_exit(&dev->low_mutex); in audigyls_read_ac97() 216 mutex_enter(&dev->low_mutex); in audigyls_write_ac97() 223 mutex_exit(&dev->low_mutex); in audigyls_write_ac97() [all …]
/illumos-gate/usr/src/uts/common/io/ib/adapters/tavor/
H A D	tavor_ioctl.c	50 * (DEBUG-only), and VTS interfaces) 146 if (instance == -1) { in tavor_ioctl() 226 mutex_enter(&state->ts_fw_flashlock); in tavor_ioctl_flash_read() 227 if ((state->ts_fw_flashdev != dev) \|\| in tavor_ioctl_flash_read() 228 (state->ts_fw_flashstarted == 0)) { in tavor_ioctl_flash_read() 229 mutex_exit(&state->ts_fw_flashlock); in tavor_ioctl_flash_read() 240 mutex_exit(&state->ts_fw_flashlock); in tavor_ioctl_flash_read() 251 mutex_exit(&state->ts_fw_flashlock); in tavor_ioctl_flash_read() 262 (state->ts_fw_device_sz >> state->ts_fw_log_sector_sz)) { in tavor_ioctl_flash_read() 263 mutex_exit(&state->ts_fw_flashlock); in tavor_ioctl_flash_read() [all …]
/illumos-gate/usr/src/uts/common/sys/audio/
H A D	ac97.h	39 * This header file describes the AC-97 Codec register set. See the 47 /* Reset Register Index 00h / 71 / Headphone Volume Register Index 04h - Optional / 81 / Mono Master Volume Register Index 06h - Optional / 88 / Master Tone Control Register Index 08h - Optional / 97 / PC Beep Register Index 0ah - Optional / 103 / Phone Volume Register Index 0ch - Optional / 139 / Video Volume Register Index 14h - Optional / 149 / Aux Volume Register Index 16h - Optional / 199 / Record Gain Mic Register Index 1eh - Optional */ [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/illumos-gate/usr/src/uts/common/io/arn/
H A D	arn_hw.c	63 if (ah->ah_curchan != NULL) in ath9k_hw_mac_usec() 65 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)]); in ath9k_hw_mac_usec() 73 struct ath9k_channel chan = ah->ah_curchan; in ath9k_hw_mac_to_usec() 84 if (ah->ah_curchan != NULL) in ath9k_hw_mac_clks() 86 ah->ah_curchan)]); in ath9k_hw_mac_clks() 94 struct ath9k_channel chan = ah->ah_curchan; in ath9k_hw_mac_to_clks() 149 struct ath9k_hw_capabilities pCap = &ah->ah_caps; in ath9k_get_channel_edges() 152 low = pCap->low_5ghz_chan; in ath9k_get_channel_edges() 153 high = pCap->high_5ghz_chan; in ath9k_get_channel_edges() 157 low = pCap->low_2ghz_chan; in ath9k_get_channel_edges() [all …]
H A D	arn_ath9k.h	133 #define ATH9K_RXKEYIX_INVALID ((uint8_t)-1) 134 #define ATH9K_TXKEYIX_INVALID ((uint32_t)-1) 333 #define ATH9K_TXQ_USEDEFAULT ((uint32_t)(-1)) 422 ATH9K_INT_NOCARD = -1 496 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) \|\| \ 497 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) \|\| \ 498 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) \|\| \ 499 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) 500 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) \|\| \ 501 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) \|\| \ [all …]
/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A D	xgehal-device.c	`21 * Copyright (c) 2002-2006 Neterion, Inc. 29 #include "xgehal-device.h" 30 #include "xgehal-channel.h" 31 #include "xgehal-fifo.h" 32 #include "xgehal-ring.h" 33 #include "xgehal-driver.h" 34 #include "xgehal-mgmt.h" 52 a -= b; a -= c; a ^= (c>>13); \ 53 b - [all...]`
/illumos-gate/usr/src/uts/common/io/efe/
H A D	efe.h	76 #define CSR_NVCTL 0x10 /* Non-volatile Control Register / 162 #define INTSTAT_GP2 (1UL << 15) / GPIO Event / 190 #define INTMASK_GP2 (1UL << 15) / GPIO Event / 192 #define GENCTL_RESET (1UL << 0) / Soft Reset / 208 #define GENCTL_RSTPHY (1UL << 14) / PHY Reset / 210 #define GENCTL_RD (1UL << 17) / Reset Disable / 226 #define NVCTL_IPG_DLY 7 / Inter-packet Gap Timer Delay / 291 #define TXSTAT_ND (1UL << 1) / Non-deferred Transmission */ 313 ddi_get32((efep)->efe_regs_acch, \ 314 (efep)->efe_regs + ((reg) / sizeof (uint32_t))) [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/
H A D	dev_info.h	94 /* Up to 16 bytes of NULL-terminated string / 113 (if multiple found, priority order is: NC-SI, UMP, IPMI) / 118 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 119 (can only be used when an add-in board, not BMC, pulls-down SPIO4) / 121 / Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 122 (can only be used when an add-in board, not BMC, pulls-down SPIO4) / 124 / Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 125 (can only be used when an add-in board, not BMC, pulls-down SPIO4) / 255 / Reserved bits: 226-230 / 371 / Default values: 2P-64, 4P-32 */ [all …]
/illumos-gate/usr/src/uts/common/io/chxge/com/
H A D	vsc7326_reg.h	23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 31 * Straight off the data sheet, VMDS-10038 Rev 2.0 and 32 * PD0011-01-14-Meigs-II 2002-12-12 42 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset / 51 #define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) / GPIO Control / 52 #define REG_GPIO_OUT CRA(0x7,0xf,0x1e) / GPIO Out / 53 #define REG_GPIO_IN CRA(0x7,0xf,0x1f) / GPIO In / 92 fn = FIFO number, 0-9 107 * bn = bucket number 0-10 (yes, 11 buckets) 137 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */ [all …]
H A D	vsc7321_reg.h	23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 31 * Straight off the data sheet, VMDS-10038 Rev 2.0 and 32 * PD0011-01-14-Meigs-II 2002-12-12 42 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset / 49 #define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) / GPIO Control / 50 #define REG_GPIO_OUT CRA(0x7,0xf,0x1e) / GPIO Out / 51 #define REG_GPIO_IN CRA(0x7,0xf,0x1f) / GPIO In / 88 fn = FIFO number, 0-9 101 * bn = bucket number 0-10 (yes, 11 buckets) 131 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */ [all …]
/illumos-gate/usr/src/uts/sun4u/excalibur/io/
H A D	xcalppm.c	31 * Platform Power Management driver for SUNW,Sun-Blade-1000 118 * one-to-one correspondence with the cpu_level array. 182 nodev, /* reset / 192 &mod_driverops, / type of module - pseudo / 244 &unitp->hndls.bbc_estar_ctrl); in xcppm_map_all_regs() 246 unitp->regs.bbc_estar_ctrl = (uint16_t )(base_addr + in xcppm_map_all_regs() 248 unitp->regs.bbc_assert_change = (uint32_t )(base_addr + in xcppm_map_all_regs() 250 unitp->regs.bbc_pll_settle = (uint32_t )(base_addr + in xcppm_map_all_regs() 254 (caddr_t *)&unitp->regs.rio_mode_auxio, in xcppm_map_all_regs() 255 0, 0, &attr_le, &unitp->hndls.rio_mode_auxio); in xcppm_map_all_regs() [all …]

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