Home
last modified time | relevance | path

Searched full:ref_clk (Results 1 – 25 of 122) sorted by relevance

12345

/linux/Documentation/devicetree/bindings/net/
H A Dnxp,tja11xx.yaml52 The REF_CLK is provided for both transmitted and received data
56 connected to pin REF_CLK. A third option is to connect a 25MHz
57 clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
59 If present, indicates that the REF_CLK will be configured as
61 If not present, the REF_CLK will be configured as interface
79 description: Enable 50MHz RMII reference clock output on REF_CLK pin.
/linux/Documentation/devicetree/bindings/clock/
H A Dcirrus,cs2000-cp.yaml25 Common clock binding for CLK_IN, XTI/REF_CLK
31 - const: ref_clk
44 - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
61 output signal directly from the REF_CLK input.
87 clock-names = "clk_in", "ref_clk";
/linux/drivers/gpu/drm/mgag200/
H A Dmgag200_g200.c83 long ref_clk = g200->ref_clk; in mgag200_g200_pixpllc_atomic_check() local
106 computed = ref_clk * (testn + 1) / (testm + 1); in mgag200_g200_pixpllc_atomic_check()
118 f_vco = ref_clk * n / m; in mgag200_g200_pixpllc_atomic_check()
300 g200->ref_clk = 14318; in mgag200_g200_interpret_bios()
306 g200->ref_clk = 14318; in mgag200_g200_interpret_bios()
315 g200->ref_clk = 14318; in mgag200_g200_interpret_bios()
333 g200->ref_clk = 27050; in mgag200_g200_init_refclk()
347 drm_dbg_kms(dev, "pclk_min: %ld pclk_max: %ld ref_clk: %ld\n", in mgag200_g200_init_refclk()
348 g200->pclk_min, g200->pclk_max, g200->ref_clk); in mgag200_g200_init_refclk()
/linux/drivers/clk/
H A Dclk-cs2000-cp.c75 #define REF_CLK 1 macro
106 struct clk *ref_clk; member
425 * In static mode, CLK_IN is ignored, so we return REF_CLK instead. in cs2000_get_parent()
427 return priv->dynamic_mode ? CLK_IN : REF_CLK; in cs2000_get_parent()
442 struct clk *clk_in, *ref_clk; in cs2000_clk_get() local
449 ref_clk = devm_clk_get(dev, "ref_clk"); in cs2000_clk_get()
451 if (IS_ERR(ref_clk)) in cs2000_clk_get()
455 priv->ref_clk = ref_clk; in cs2000_clk_get()
486 ref_clk_rate = clk_get_rate(priv->ref_clk); in cs2000_clk_register()
506 parent_names[REF_CLK] = __clk_get_name(priv->ref_clk); in cs2000_clk_register()
H A Dclk-moxart.c20 struct clk *ref_clk; in moxart_of_pll_clk_init() local
37 ref_clk = of_clk_get(node, 0); in moxart_of_pll_clk_init()
38 if (IS_ERR(ref_clk)) { in moxart_of_pll_clk_init()
/linux/Documentation/devicetree/bindings/usb/
H A Drockchip,dwc3.yaml71 - const: ref_clk
113 - const: ref_clk
129 - const: ref_clk
156 - const: ref_clk
177 clock-names = "ref_clk", "suspend_clk",
/linux/drivers/phy/hisilicon/
H A Dphy-hisi-inno-usb2.c52 struct clk *ref_clk; member
100 ret = clk_prepare_enable(priv->ref_clk); in hisi_inno_phy_init()
124 clk_disable_unprepare(priv->ref_clk); in hisi_inno_phy_exit()
154 priv->ref_clk = devm_clk_get(dev, NULL); in hisi_inno_phy_probe()
155 if (IS_ERR(priv->ref_clk)) in hisi_inno_phy_probe()
156 return PTR_ERR(priv->ref_clk); in hisi_inno_phy_probe()
H A Dphy-histb-combphy.c48 struct clk *ref_clk; member
121 ret = clk_prepare_enable(priv->ref_clk); in histb_combphy_init()
154 clk_disable_unprepare(priv->ref_clk); in histb_combphy_exit()
244 priv->ref_clk = devm_clk_get(dev, NULL); in histb_combphy_probe()
245 if (IS_ERR(priv->ref_clk)) { in histb_combphy_probe()
247 return PTR_ERR(priv->ref_clk); in histb_combphy_probe()
/linux/drivers/phy/samsung/
H A Dphy-samsung-usb2.c36 ret = clk_prepare_enable(drv->ref_clk); in samsung_usb2_phy_power_on()
50 clk_disable_unprepare(drv->ref_clk); in samsung_usb2_phy_power_on()
75 clk_disable_unprepare(drv->ref_clk); in samsung_usb2_phy_power_off()
199 drv->ref_clk = devm_clk_get(dev, "ref"); in samsung_usb2_phy_probe()
200 if (IS_ERR(drv->ref_clk)) { in samsung_usb2_phy_probe()
202 return PTR_ERR(drv->ref_clk); in samsung_usb2_phy_probe()
205 drv->ref_rate = clk_get_rate(drv->ref_clk); in samsung_usb2_phy_probe()
/linux/drivers/rtc/
H A Drtc-cadence.c82 struct clk *ref_clk; member
281 crtc->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); in cdns_rtc_probe()
282 if (IS_ERR(crtc->ref_clk)) { in cdns_rtc_probe()
283 ret = PTR_ERR(crtc->ref_clk); in cdns_rtc_probe()
302 ret = clk_prepare_enable(crtc->ref_clk); in cdns_rtc_probe()
309 ref_clk_freq = clk_get_rate(crtc->ref_clk); in cdns_rtc_probe()
349 clk_disable_unprepare(crtc->ref_clk); in cdns_rtc_probe()
365 clk_disable_unprepare(crtc->ref_clk); in cdns_rtc_remove()
/linux/include/linux/platform_data/
H A Dnet-cw1200.h13 u16 ref_clk; /* REQUIRED (in KHz) */ member
26 u16 ref_clk; /* REQUIRED (in KHz) */ member
44 .ref_clk = 38400,
67 .ref_clk = 38400,
/linux/drivers/phy/
H A Dphy-snps-eusb2.c167 struct clk *ref_clk; member
249 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); in exynos_eusb2_ref_clk_init()
286 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); in qcom_eusb2_ref_clk_init()
331 /* update ref_clk related registers */ in exynos_snps_eusb2_hsphy_init()
388 /* update ref_clk related registers */ in qcom_snps_eusb2_hsphy_init()
566 phy->ref_clk = NULL; in snps_eusb2_hsphy_probe()
569 phy->ref_clk = phy->clks[i].clk; in snps_eusb2_hsphy_probe()
574 if (IS_ERR_OR_NULL(phy->ref_clk)) { in snps_eusb2_hsphy_probe()
575 ret = phy->ref_clk ? PTR_ERR(phy->ref_clk) : -ENOENT; in snps_eusb2_hsphy_probe()
/linux/Documentation/devicetree/bindings/phy/
H A Damlogic,g12a-usb3-pcie-phy.yaml26 - const: ref_clk
59 clocks = <&ref_clk>;
60 clock-names = "ref_clk";
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-ipq806x-usb.c122 struct clk *ref_clk; member
262 ret = clk_prepare_enable(phy_dwc3->ref_clk); in qcom_ipq806x_usb_hs_phy_init()
295 clk_disable_unprepare(phy_dwc3->ref_clk); in qcom_ipq806x_usb_hs_phy_exit()
311 ret = clk_prepare_enable(phy_dwc3->ref_clk); in qcom_ipq806x_usb_ss_phy_init()
448 clk_disable_unprepare(phy_dwc3->ref_clk); in qcom_ipq806x_usb_ss_phy_exit()
509 phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref"); in qcom_ipq806x_usb_phy_probe()
510 if (IS_ERR(phy_dwc3->ref_clk)) { in qcom_ipq806x_usb_phy_probe()
512 return PTR_ERR(phy_dwc3->ref_clk); in qcom_ipq806x_usb_phy_probe()
515 clk_set_rate(phy_dwc3->ref_clk, data->clk_rate); in qcom_ipq806x_usb_phy_probe()
H A Dphy-qcom-usb-hs.c32 struct clk *ref_clk; member
115 ret = clk_prepare_enable(uphy->ref_clk); in qcom_usb_hs_phy_power_on()
176 clk_disable_unprepare(uphy->ref_clk); in qcom_usb_hs_phy_power_on()
190 clk_disable_unprepare(uphy->ref_clk); in qcom_usb_hs_phy_power_off()
232 uphy->ref_clk = clk = devm_clk_get(&ulpi->dev, "ref"); in qcom_usb_hs_phy_probe()
H A Dphy-qcom-qusb2.c437 * @ref_clk: phy reference clock
457 struct clk *ref_clk; member
689 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
723 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
828 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
829 * ref_clk only. in qusb2_phy_init()
851 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
887 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
909 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
1012 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi.c110 struct clk *ref_clk; in mtk_mipi_tx_probe() local
132 ref_clk = devm_clk_get(dev, NULL); in mtk_mipi_tx_probe()
133 if (IS_ERR(ref_clk)) in mtk_mipi_tx_probe()
134 return dev_err_probe(dev, PTR_ERR(ref_clk), in mtk_mipi_tx_probe()
151 ref_clk_name = __clk_get_name(ref_clk); in mtk_mipi_tx_probe()
H A Dphy-mtk-xsphy.c96 struct clk *ref_clk; /* reference clock of anolog phy */ member
386 ret = clk_prepare_enable(inst->ref_clk); in mtk_phy_init()
388 dev_err(xsphy->dev, "failed to enable ref_clk\n"); in mtk_phy_init()
406 clk_disable_unprepare(inst->ref_clk); in mtk_phy_init()
441 clk_disable_unprepare(inst->ref_clk); in mtk_phy_exit()
587 inst->ref_clk = devm_clk_get(&phy->dev, "ref"); in mtk_xsphy_probe()
588 if (IS_ERR(inst->ref_clk)) { in mtk_xsphy_probe()
589 dev_err(dev, "failed to get ref_clk(id-%d)\n", port); in mtk_xsphy_probe()
590 return PTR_ERR(inst->ref_clk); in mtk_xsphy_probe()
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-rx.c65 struct clk *ref_clk; member
123 clk_set_rate(dphy->ref_clk, 49500000); in stf_dphy_power_on()
171 dphy->ref_clk = devm_clk_get(&pdev->dev, "ref"); in stf_dphy_probe()
172 if (IS_ERR(dphy->ref_clk)) in stf_dphy_probe()
173 return PTR_ERR(dphy->ref_clk); in stf_dphy_probe()
/linux/drivers/spi/
H A Dspi-cadence.c104 * @ref_clk: Pointer to the peripheral clock
106 * @clk_rate: Reference clock frequency, taken from @ref_clk
119 struct clk *ref_clk; member
604 xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk"); in cdns_spi_probe()
605 if (IS_ERR(xspi->ref_clk)) { in cdns_spi_probe()
606 dev_err(&pdev->dev, "ref_clk clock not found.\n"); in cdns_spi_probe()
607 ret = PTR_ERR(xspi->ref_clk); in cdns_spi_probe()
661 xspi->clk_rate = clk_get_rate(xspi->ref_clk); in cdns_spi_probe()
764 ret = clk_prepare_enable(xspi->ref_clk); in cdns_spi_runtime_resume()
786 clk_disable_unprepare(xspi->ref_clk); in cdns_spi_runtime_suspend()
/linux/Documentation/devicetree/bindings/rtc/
H A Dcdns,rtc.txt12 - ref_clk: reference 1Hz or 100Hz clock, depending on IP configuration
20 clock-names = "pclk", "ref_clk";
/linux/Documentation/devicetree/bindings/spi/
H A Djcore,spi.txt15 - clocks: If a phandle named "ref_clk" is present, SPI clock speed
33 clock-names = "ref_clk";
H A Dxlnx,zynq-qspi.yaml37 - const: ref_clk
56 clock-names = "ref_clk", "pclk";
/linux/Documentation/devicetree/bindings/fpga/
H A Dxilinx-zynq-fpga-mgr.yaml27 - const: ref_clk
50 clock-names = "ref_clk";
/linux/drivers/gpu/drm/radeon/
H A Drv6xx_dpm.c163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping() local
183 fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >> in rv6xx_output_stepping()
428 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay() local
430 return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit); in rv6xx_compute_count_for_delay()
551 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum() local
561 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers, in rv6xx_program_engine_spread_spectrum()
567 (ref_clk / (dividers.ref_div + 1)), in rv6xx_program_engine_spread_spectrum()
573 (ref_clk / (dividers.ref_div + 1))); in rv6xx_program_engine_spread_spectrum()
632 u32 ref_clk, in rv6xx_find_memory_clock_with_highest_vco() argument
642 vco_freq_temp = rv6xx_calculate_vco_frequency(ref_clk, &req_dividers, in rv6xx_find_memory_clock_with_highest_vco()
[all …]

12345