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/linux/drivers/clk/at91/
H A Dclk-audio-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Quentin Schulz <quentin.schulz@free-electrons.com>
10 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
11 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
12 * asked rate.
15 * enable - clk_enable writes nd, fracr parameters and enables PLL
16 * rate - rate is adjustable.
17 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
18 * parent - fixed parent. No clk_set_parent support
21 * enable - clk_enable writes qdpmc, and enables PMC output
[all …]
/linux/drivers/clk/ti/
H A Dclkt_dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
17 #include <linux/clk-provider.h>
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
30 #define DPLL_MULT_UNDERFLOW -1
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
35 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
36 * must be a power of DPLL_SCALE_BASE.
[all …]
H A Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
[all …]
H A Ddpll44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP4-specific DPLL control functions
20 * can supported when using the DPLL low-power mode. Frequencies are
22 * Status, and Low-Power Operation Mode".
34 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
45 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_allow_gatectrl()
49 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
52 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
63 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_deny_gatectrl()
67 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
48 * When we change the timing to a timing with a parent that has the same
49 * clock source as the current parent, we must first change to a backup
50 * timing that has a different clock source.
66 unsigned long rate, parent_rate; member
101 * so get the parent rate explicitly. in emc_recalc_rate()
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
112 * Rounds up unless no higher rate exists, in which case down. This way is
[all …]
/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk/clk-conf.h>
12 #include <linux/clk-provider.h>
78 unsigned long rate; member
123 if (!core->rpm_enabled) in clk_pm_runtime_get()
126 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get()
131 if (!core->rpm_enabled) in clk_pm_runtime_put()
[all …]
H A Dclk-fixed-rate_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for clk fixed rate basic type
6 #include <linux/clk-provider.h>
17 #include "clk-fixed-rate_test.h"
20 * struct clk_hw_fixed_rate_kunit_params - Parameters to pass to __clk_hw_register_fixed_rate()
30 * @clk_fixed_flags: fixed rate specific clk flags
51 hw = __clk_hw_register_fixed_rate(params->dev, params->np, in clk_hw_register_fixed_rate_kunit_init()
52 params->name, in clk_hw_register_fixed_rate_kunit_init()
53 params->parent_name, in clk_hw_register_fixed_rate_kunit_init()
54 params->parent_hw, in clk_hw_register_fixed_rate_kunit_init()
[all …]
/linux/net/ipv4/
H A Dtcp_rate.c1 // SPDX-License-Identifier: GPL-2.0-only
4 /* The bandwidth estimator estimates the rate at which the network
5 * can currently deliver outbound data packets for this flow. At a high
6 * level, it operates by taking a delivery rate sample for each ACK.
8 * A rate sample records the rate at which the network delivered packets
10 * of a data packet and the acknowledgment of that packet.
13 * the estimator generates a delivery rate sample. Typically it uses the rate
15 * acknowledgment rate faces a challenge under the prevalent ACK decimation or
17 * than the bottleneck rate. Since it is physically impossible to do that in a
18 * sustained fashion, when the estimator notices that the ACK rate is faster
[all …]
/linux/net/core/
H A Dgen_estimator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * net/sched/gen_estimator.c Simple rate estimator.
9 * Jamal Hadi Salim - moved it to net/core and reshulfed
36 * its purpose is to provide a base for statistical multiplexing
38 * If you need only statistics, run a user level daemon which
66 if (e->stats_lock) in est_fetch_counters()
67 spin_lock(e->stats_lock); in est_fetch_counters()
69 gnet_stats_add_basic(b, e->cpu_bstats, e->bstats, e->running); in est_fetch_counters()
71 if (e->stats_lock) in est_fetch_counters()
72 spin_unlock(e->stats_lock); in est_fetch_counters()
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
37 /* Normalize value to a 6M multiple */ in sun4i_get_pll1_factors()
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
[all …]
/linux/drivers/gpu/drm/tests/
H A Ddrm_connector_test.c1 // SPDX-License-Identifier: GPL-2.0
74 strscpy(priv->ddc.name, "dummy-connector-ddc", sizeof(priv->ddc.name)); in drm_test_connector_init()
75 priv->ddc.owner = THIS_MODULE; in drm_test_connector_init()
76 priv->ddc.algo = &dummy_ddc_algorithm; in drm_test_connector_init()
77 priv->ddc.dev.parent = dev; in drm_test_connector_init()
79 ret = i2c_add_adapter(&priv->ddc); in drm_test_connector_init()
82 ret = kunit_add_action_or_reset(test, i2c_del_adapter_wrapper, &priv->ddc); in drm_test_connector_init()
85 test->priv = priv; in drm_test_connector_init()
90 * Test that the registration of a bog standard connector works as
95 struct drm_connector_init_priv *priv = test->priv; in drm_test_drmm_connector_init()
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2003 - 2014, 2018 - 2025 Intel Corporation
14 #include "iwl-config.h"
16 #include "fw-api.h"
17 #include "iwl-trans.h"
19 #define RS_NAME "iwl-mvm-rs"
27 u8 prev_rs; /* previous rate used in rs algo */
28 u8 next_rs; /* next rate used in rs algo */
48 IWL_RATE_INVM_INDEX_TABLE = IWL_RATE_INVM_INDEX - 1,
115 #define IWL_RATES_MASK ((1 << IWL_RATE_COUNT) - 1)
[all …]
/linux/arch/mips/alchemy/common/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0
8 * - Root source, usually 12MHz supplied by an external crystal
9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
12 * - 6 clock dividers with:
18 * - up to 6 "internal" (fixed) consumers which:
24 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
25 * depends on board design and should be set by bootloader, read-only.
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
27 * of peripheral blocks, read-only.
28 * - memory clock: clk rate to main memory chips, depends on board
[all …]
/linux/sound/firewire/fireface/
H A Dff-protocol-latter.c1 // SPDX-License-Identifier: GPL-2.0
2 // ff-protocol-latter.c - a part of driver for RME Fireface series
20 // 0x0f000000: effective rate of sampling clock
21 // 0x00f00000: detected rate of word clock on BNC interface
22 // 0x000f0000: detected rate of ADAT or S/PDIF on optical interface
23 // 0x0000f000: detected rate of S/PDIF on coaxial interface
41 // 0xf0000000: effective rate of sampling clock
42 // 0x0f000000: detected rate of ADAT-B on 2nd optical interface
43 // 0x00f00000: detected rate of ADAT-A on 1st optical interface
44 // 0x000f0000: detected rate of AES/EBU on XLR or coaxial interface
[all …]
/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965-rs.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 #define IL4965_RS_NAME "iwl-4965-rs"
35 /* max allowed rate miss before sync LQ cmd */
51 /*ANT_NONE -> */ ANT_NONE,
52 /*ANT_A -> */ ANT_B,
53 /*ANT_B -> */ ANT_C,
54 /*ANT_AB -> */ ANT_BC,
55 /*ANT_C -> */ ANT_A,
[all …]
/linux/drivers/clk/bcm/
H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
16 * "Policies" affect the frequencies of bus clocks provided by a
18 * "Normal", and "Turbo".) A lower policy number has lower power
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
34 /* Extract the value of a bitfield found within a given register value */
40 /* Replace the value of a bitfield found within a given register value */
50 /* Convert a divider into the scaled divisor value it represents. */
[all …]
/linux/Documentation/misc-devices/
H A Doxsemi-tornado.rst1 .. SPDX-License-Identifier: GPL-2.0
8 by a fixed 62.5MHz clock input derived from the 100MHz PCI Express clock.
10 The baud rate produced by the baud generator is obtained from this input
12 value from 1 to 63.875 in increments of 0.125, and then the usual 16-bit
13 divisor is used as with the original 8250, to divide the frequency by a
14 value from 1 to 65535. Finally a programmable oversampling rate is used
16 determine the actual baud rate used. Baud rates from 15625000bps down
19 By default the oversampling rate is set to 16 and the clock prescaler is
21 for the usual 16-bit divisor is 115313.653, which is close enough to the
26 The oversampling rate is programmed with the TCR register and the clock
[all …]
/linux/drivers/iio/health/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 menu "Heart Rate Monitors"
12 tristate "TI AFE4403 Heart Rate Monitor"
19 heart rate monitor and low-cost pulse oximeter.
21 To compile this driver as a module, choose M here: the
25 tristate "TI AFE4404 heart rate and pulse oximeter sensor"
32 heart rate monitor and low-cost pulse oximeter.
34 To compile this driver as a module, choose M here: the
38 tristate "MAX30100 heart rate and pulse oximeter sensor"
45 MAX30100 heart rate, and pulse oximeter sensor.
[all …]
/linux/drivers/clk/zynqmp/
H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
22 * parent - fixed parent. No clk_set_parent support
28 #define CLK_FRAC BIT(13) /* has a fractional parent */
29 #define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
[all …]
/linux/drivers/clk/keystone/
H A Dsci-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
8 #include <linux/clk-provider.h>
24 * struct sci_clk_provider - TI SCI clock provider representation
40 * struct sci_clk - TI SCI clock representation
48 * @cached_req: Cached requested freq for determine rate calls
49 * @cached_res: Cached result freq for determine rate calls
66 * sci_clk_prepare - Prepare (enable) a TI SCI clock
69 * Prepares a clock to be actively used. Returns the SCI protocol status.
[all …]
/linux/drivers/memory/tegra/
H A Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
181 unsigned long rate; member
217 * a min/max clock rate, these rates are contained in this array.
221 /* protect shared rate-change code path */
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
257 unsigned long rate) in tegra_emc_find_timing() argument
262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
[all …]
/linux/Documentation/networking/devlink/
H A Dnetdevsim.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 * - ``max_macs``
18 - driverinit
20 The ``netdevsim`` driver also implements the following driver-specific
23 .. list-table:: Driver-specific parameters implemented
26 * - Name
27 - Type
[all …]
/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpllcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
30 #include "cm-regbits-24xx.h"
44 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
46 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
47 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
49 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
72 * Uses the current prcm set to tell if a rate is valid.
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/dvm/
H A Drs.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
5 * Copyright (C) 2019 - 2020, 2022 - 2023 Intel Corporation
21 #define RS_NAME "iwl-agn-rs"
31 /* max allowed rate miss before sync LQ cmd */
47 /*ANT_NONE -> */ ANT_NONE,
48 /*ANT_A -> */ ANT_B,
49 /*ANT_B -> */ ANT_C,
50 /*ANT_AB -> */ ANT_BC,
51 /*ANT_C -> */ ANT_A,
[all …]
/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dtc_restrictions.sh2 # SPDX-License-Identifier: GPL-2.0
41 # It is forbidden in mlxsw driver to have mixed-bound
42 # shared block with a drop rule.
90 # egress-bound block.
145 # actions in a single rule.
172 # bound on egress. Spectrum-1 specific restriction
178 matchall skip_sw action sample rate 100 group 1
184 matchall skip_sw action sample rate 100 group 1
199 # On ingress, all matchall-mirror and matchall-sample
209 check_err $? "Failed to add matchall rule in front of a flower rule"
[all …]

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