Lines Matching +full:rate +full:- +full:a
1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP4-specific DPLL control functions
20 * can supported when using the DPLL low-power mode. Frequencies are
22 * Status, and Low-Power Operation Mode".
34 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
45 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_allow_gatectrl()
49 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
52 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
63 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_deny_gatectrl()
67 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
70 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
82 * Calculates if low-power mode can be enabled based upon the last
83 * multiplier and divider values calculated. If low-power mode can be
84 * enabled, then the bit to enable low-power mode is stored in the
86 * criteria for enabling low-power mode as described in the OMAP4430/60
87 * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
94 fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); in omap4_dpll_lpmode_recalc()
95 fout = fint * dd->last_rounded_m; in omap4_dpll_lpmode_recalc()
98 dd->last_rounded_lpmode = 1; in omap4_dpll_lpmode_recalc()
100 dd->last_rounded_lpmode = 0; in omap4_dpll_lpmode_recalc()
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
105 * @hw: pointer to the clock to compute the rate for
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
118 unsigned long rate; in omap4_dpll_regm4xen_recalc() local
121 if (!clk || !clk->dpll_data) in omap4_dpll_regm4xen_recalc()
124 dd = clk->dpll_data; in omap4_dpll_regm4xen_recalc()
126 rate = omap2_get_dpll_rate(clk); in omap4_dpll_regm4xen_recalc()
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
129 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap4_dpll_regm4xen_recalc()
131 rate *= OMAP4430_REGM4XEN_MULT; in omap4_dpll_regm4xen_recalc()
133 return rate; in omap4_dpll_regm4xen_recalc()
137 * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
138 * @hw: pointer to the clock to determine rate for
139 * @req: target rate request
141 * Determines which DPLL mode to use for reaching a desired rate.
144 * Returns 0 on success and a negative error value otherwise.
152 if (!req->rate) in omap4_dpll_regm4xen_determine_rate()
153 return -EINVAL; in omap4_dpll_regm4xen_determine_rate()
155 dd = clk->dpll_data; in omap4_dpll_regm4xen_determine_rate()
157 return -EINVAL; in omap4_dpll_regm4xen_determine_rate()
159 if (clk_hw_get_rate(dd->clk_bypass) == req->rate && in omap4_dpll_regm4xen_determine_rate()
160 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { in omap4_dpll_regm4xen_determine_rate()
161 req->best_parent_hw = dd->clk_bypass; in omap4_dpll_regm4xen_determine_rate()
166 clk_hw_init_rate_request(hw, &tmp_req, req->rate); in omap4_dpll_regm4xen_determine_rate()
167 dd->last_rounded_m4xen = 0; in omap4_dpll_regm4xen_determine_rate()
171 * target rate without using the 4X multiplier. in omap4_dpll_regm4xen_determine_rate()
177 * If we did not find a valid DPLL configuration, try again, but in omap4_dpll_regm4xen_determine_rate()
179 * 4X multiplier is equivalent to dividing the target rate by 4. in omap4_dpll_regm4xen_determine_rate()
181 tmp_req.rate /= OMAP4430_REGM4XEN_MULT; in omap4_dpll_regm4xen_determine_rate()
186 dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; in omap4_dpll_regm4xen_determine_rate()
187 dd->last_rounded_m4xen = 1; in omap4_dpll_regm4xen_determine_rate()
192 req->rate = dd->last_rounded_rate; in omap4_dpll_regm4xen_determine_rate()
193 req->best_parent_hw = dd->clk_ref; in omap4_dpll_regm4xen_determine_rate()
196 req->best_parent_rate = req->rate; in omap4_dpll_regm4xen_determine_rate()