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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx-pinctrl.txt7 different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
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H A Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Multiplexing Node
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
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H A Dfsl,imx7d-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
19 - enum:
20 - fsl,imx7d-iomuxc
21 - fsl,imx7d-iomuxc-lpsr
26 fsl,input-sel:
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H A Dbrcm,nsp-gpio.txt4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
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H A Dcirrus,madera.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
30 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
33 pin-settings:
35 One subnode is required to contain the default settings. It
37 each group or pin configuration you want to apply as a default.
40 '-pins$':
43 - $ref: pincfg-node.yaml#
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H A Dmediatek,mt6779-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT6779 Pin Controller
10 - Andy Teng <andy.teng@mediatek.com>
11 - Sean Wang <sean.wang@kernel.org>
14 The MediaTek pin controller on MT6779 is used to control pin functions, pull
20 - mediatek,mt6779-pinctrl
21 - mediatek,mt6797-pinctrl
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H A Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT6795 Pin Controller
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
14 The MediaTek's MT6795 Pin controller is used to control SoC pins.
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
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H A Dfsl,scu-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Pinctrl Based on SCU Message Protocol
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
15 (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt)
18 - $ref: pinctrl.yaml#
23 - fsl,imx8qm-iomuxc
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/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
31 * @pid: first pin id handled by this control
38 * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
40 * between two or more different settings, e.g. assign mpp pin 13 to
45 * to allow pin settings with varying gpio pins.
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
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H A Dpinctrl-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
24 #include "pinctrl-mvebu.h"
40 struct mvebu_mpp_ctrl_setting *settings; member
64 *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; in mvebu_mmio_mpp_ctrl_get()
76 reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); in mvebu_mmio_mpp_ctrl_set()
77 writel(reg | (config << shift), data->base + off); in mvebu_mmio_mpp_ctrl_set()
86 for (n = 0; n < pctl->num_groups; n++) { in mvebu_pinctrl_find_group_by_pid()
87 if (pid >= pctl->groups[n].pins[0] && in mvebu_pinctrl_find_group_by_pid()
88 pid < pctl->groups[n].pins[0] + in mvebu_pinctrl_find_group_by_pid()
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/linux/Documentation/arch/arm/pxa/
H A Dmfp.rst7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
14 Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
18 detection of each pin. Below is a diagram of internal connections between
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
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/linux/drivers/pinctrl/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
31 * @node: node to include this pin controller in the global pin controller list
32 * @desc: the pin controller descriptor supplied when initializing this pin
34 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
36 * @pin_group_tree: optionally each pin group can be stored in this radix tree
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H A Dpinctrl-axp209.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
6 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
23 #include <linux/pinctrl/pinconf-generic.h>
52 /* Stores the pins supporting LDO function. Bit offset is pin number. */
54 /* Stores the pins supporting ADC function. Bit offset is pin number. */
124 return -EINVAL; in axp20x_gpio_get_reg()
133 /* AXP209 has GPIO3 status sharing the settings register */ in axp20x_gpio_get()
135 ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val); in axp20x_gpio_get()
141 ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val); in axp20x_gpio_get()
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H A Dpinconf.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin config portions of the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
29 const struct pinconf_ops *ops = pctldev->desc->confops; in pinconf_check_ops()
32 if (!ops->pin_config_set && !ops->pin_config_group_set) { in pinconf_check_ops()
33 dev_err(pctldev->dev, in pinconf_check_ops()
35 return -EINVAL; in pinconf_check_ops()
42 if (!map->data.configs.group_or_pin) { in pinconf_validate_map()
43 pr_err("failed to register map %s (%d): no group/pin given\n", in pinconf_validate_map()
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
51 /* Global list of pin control devices (struct pinctrl_dev) */
54 /* List of pin controller handles (struct pinctrl) */
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
89 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
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/linux/include/linux/ssb/
H A Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
192 #define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
210 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
211 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
214 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
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/linux/Documentation/driver-api/
H A Dpin-control.rst2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
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/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
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/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu9_driver_if.h46 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
47 #define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
48 #define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
49 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
51 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
52 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
65 #define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
142 /* External Component Communication Settings */
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/linux/drivers/media/rc/
H A Dnuvoton-cir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
18 #define NVT_DRIVER_NAME "nuvoton-cir"
71 /* hardware I/O settings */
91 /* CIR settings */
117 /* CIR IRCON settings */
134 /* CIR IRSTS settings */
144 /* CIR IREN settings */
154 /* CIR FIFOCON settings */
177 /* CIR IRFIFOSTS settings */
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/linux/drivers/soc/pxa/
H A Dmfp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/plat-pxa/mfp.c
5 * Multi-Function Pin Support
9 * 2007-08-21: eric miao <eric.miao@marvell.com>
42 * Table that determines the low power modes outputs, with actual settings
43 * used in parentheses for don't-care values. Except for the float output,
45 * non-LPM pulled output, the same configuration could probably be used.
66 * The pullup and pulldown state of the MFP pin at run mode is by default
85 * (most likely a read-modify-write operation) is atomic, and that
93 unsigned long config; /* -1 for not configured */
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/linux/Documentation/devicetree/bindings/soc/renesas/
H A Drenesas,r9a09g011-sys.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g011-sys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The RZ/V2M-alike SYS (System Configuration) controls the overall
15 - Bank address settings for DMAC
16 - Bank address settings of the units for ICB
17 - ETHER AxCACHE[1] (C bit) control function
18 - RAMA initialization control
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/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dsis_i2c.txt4 - compatible: must be "sis,9200-ts"
5 - reg: i2c slave address
6 - interrupts: touch controller interrupt (see interrupt
10 - pinctrl-names: should be "default" (see pinctrl binding [1]).
11 - pinctrl-0: a phandle pointing to the pin settings for the
13 - attn-gpios: the gpio pin used as attention line
14 - reset-gpios: the gpio pin used to reset the controller
15 - wakeup-source: touchscreen can be used as a wakeup source
17 [0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
18 [1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dadi,ltc4282.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sa <nuno.sa@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4282.pdf
20 - adi,ltc4282
25 vdd-supply: true
30 '#clock-cells':
33 adi,rsense-nano-ohms:
36 adi,vin-mode-microvolt:
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/linux/Documentation/dev-tools/
H A Dgpio-sloppy-logic-analyzer.rst1 .. SPDX-License-Identifier: GPL-2.0
12 This document briefly describes how to run the GPIO based in-kernel sloppy
22 Another feature is to snoop on on-chip peripherals if the I/O cells of these
25 I2C traffic without any wiring (if your hardware supports it). In the pin
26 control subsystem such pin controllers are called "non-strict": a certain pin
31 non-deterministic code paths and non-maskable interrupts. It is called 'sloppy'
41 sloppy logic analyzer does not interfere with your other settings.
47 i2c-analyzer {
48 compatible = "gpio-sloppy-logic-analyzer";
49 probe-gpios = <&gpio6 21 GPIO_OPEN_DRAIN>, <&gpio6 4 GPIO_OPEN_DRAIN>;
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