| /illumos-gate/usr/src/man/man1/ |
| H A D | sar.1 | 9 sar \- system activity reporter
13 \fBsar\fR [\fB-aAbcdgkmpqruvwy\fR] [\fB-o\fR \fIfilename\fR] \fIt\fR [\fIn\fR]
18 \fBsar\fR [\fB-aAbcdgkmpqruvwy\fR] [\fB-e\fR \fItime\fR] [\fB-f\fR \fIfilename\fR] [\fB-i\fR \fIsec…
19 [\fB-s\fR \fItime\fR]
29 itself can affect the sample.) If the \fB-o\fR option is specified, it saves
36 \fB-f\fR option or, by default, the standard system activity daily data file
38 ending times of the report can be bounded using the \fB-e\fR and \fB-s\fR
40 The \fB-i\fR option selects records at \fIsec\fR second intervals. Otherwise,
48 \fB\fB-a\fR\fR
57 \fB\fB-A\fR\fR
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| H A D | zonestat.1 | 50 The -r option can be used to select the specific resources to be shown in
54 .Bl -tag -width Ds
58 In addition to a comma-separated list, multiple
65 .Bd -ragged -offset indent
66 .Em physical-memory ,
67 .Em virtual-memory ,
68 .Em locked-memory ,
69 .Em processor-set ,
72 .Em shm-memory ,
73 .Em shm-ids ,
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| /illumos-gate/usr/src/man/man8/ |
| H A D | mpstat.8 | 8 mpstat \- report per-processor or per-processor-set statistics
12 \fB/usr/bin/mpstat\fR [\fB-aq\fR] [\fB-p\fR | \fB-P\fR \fIset\fR] [\fB-T\fR u | d] [\fIinterval\fR …
18 The \fBmpstat\fR command reports processor statistics in tabular form. Each row
19 of the table represents the activity of one processor. The first table
21 for the preceding interval. All values are rates listed as events per second
31 <<processor 3 moved from pset: -1 to: 1>>
49 Without the \fB-a\fR option, \fBmpstat\fR reports \fBCPU\fR statistics for a
50 processor ID. With the \fB-a\fR option, \fBmpstat\fR reports \fBSET\fR
51 statistics for a processor set ID.
78 inter-processor cross-calls
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| H A D | vmstat.8 | 8 vmstat \- report virtual memory statistics
11 \fBvmstat\fR [\fB-ipqsS\fR] [\fB-T\fR u | d] [\fIdisks\fR] [\fIinterval\fR [\fIcount\fR]]
19 On \fBMP\fR (multi-processor) systems, \fBvmstat\fR averages the number of
20 \fBCPUs\fR into the output. For per-processor statistics, see \fBmpstat\fR(8).
27 Without options, \fBvmstat\fR displays a one-line summary of the virtual memory
53 \fB\fB-i\fR\fR
56 Report the number of interrupts per device. \fIcount\fR and \fIinterval\fR does
57 not apply to the \fB-i\fR option.
63 \fB\fB-p\fR\fR
74 Executable page-ins.
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| H A D | poolcfg.8 | 8 poolcfg \- create and modify resource pool configuration files
12 \fB/usr/sbin/poolcfg\fR \fB-c\fR \fIcommand\fR [\fB-d\fR | [\fIfilename\fR]]
17 \fB/usr/sbin/poolcfg\fR \fB-f\fR \fIcommand_file\fR [\fB-d\fR | [\fIfilename\fR]]
22 \fB/usr/sbin/poolcfg\fR \fB-h\fR
30 of modifications to the specified configuration file. If you use the \fB-d\fR
53 \fB\fB-c\fR \fIcommand\fR\fR
62 \fB\fB-d\fR\fR
71 \fB\fB-f\fR \fIcommand_file\fR\fR
75 editing commands, one per line.
81 \fB\fB-h\fR\fR
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| H A D | trapstat.8 | 8 trapstat \- report trap statistics
12 \fB/usr/sbin/trapstat\fR [\fB-t\fR | \fB-T\fR | \fB-e\fR \fIentry\fR]
13 [\fB-C\fR \fIprocessor_set_id\fR | \fB-c\fR \fIcpulist\fR] [\fB-P\fR] [\fB-a\fR]
14 [\fB-r\fR \fIrate\fR] [ [\fIinterval\fR [\fIcount\fR]] | \fIcommand\fR | [\fIargs\fR]]
19 \fB/usr/sbin/trapstat\fR \fB-l\fR
24 The \fBtrapstat\fR utility gathers and displays run-time trap statistics on
25 UltraSPARC-based systems. The default output is a table of trap types and
33 specified with the \fB-c\fR or \fB-C\fR option.
36 Unless the \fB-r\fR option or the \fB-a\fR option is specified, the value
37 displayed in each entry of the table corresponds to the number of traps per
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| H A D | intrstat.8 | 8 intrstat \- report interrupt statistics
12 \fB/usr/sbin/intrstat\fR [\fB-c\fR \fIcpulist\fR | \fB-C\fR \fIprocessor_set_id\fR] [\fB-T\fR u | d…
13 [\fB-x\fR \fIopt\fR[=\fIval\fR]] [\fIinterval\fR [\fIcount\fR]]
18 The \fBintrstat\fR utility gathers and displays run-time interrupt statistics.
29 implementing the driver. See \fBddi_driver_name\fR(9F). Many Sun-delivered
38 optionally specified with the \fB-c\fR or \fB-C\fR option.
41 By default, \fBintrstat\fR displays data once per second and runs indefinitely.
51 \fBintrstat\fR induces a small system-wide performance degradation. As a
52 result, only the super-user can run \fBintrstat\fR by default. The
61 \fB\fB-c\fR \fIcpulist\fR\fR
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| H A D | cpustat.8 | 5 cpustat \- monitor system behavior using CPU performance counters
9 \fBcpustat\fR \fB-c\fR \fIeventspec\fR [\fB-c\fR \fIeventspec\fR]... [\fB-p\fR \fIperiod\fR] [\fB-T…
10 [\fB-sntD\fR] [\fIinterval\fR [\fIcount\fR]]
15 \fBcpustat\fR \fB-h\fR
35 \fB\fB-c\fR \fIeventspec\fR\fR
50 You can use the \fB-h\fR option to obtain a list of available events and
64 Multiple \fB-c\fR options can be specified, in which case the command cycles
71 \fB\fB-D\fR\fR
81 \fB\fB-h\fR\fR
86 the processor-dependent counters.
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| /illumos-gate/usr/src/man/man3cpc/ |
| H A D | cpc_bind_curlwp.3cpc | 9 cpc_set_restart \- bind request sets to hardware counters
13 cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ]
49 These functions program the processor's hardware counters according to the
66 virtualized 64-bit counters initialized to the preset values specified in
83 the \fIpctx\fR-\fIid\fR pair, where \fIpctx\fR refers to a handle returned from
94 any application has bound a set to a CPU, per-\fBLWP\fR counters are
97 \fBcpc_bind_cpu()\fR invalidates all currently bound per-\fBLWP\fR counter
100 \fBprocessor_bind\fR(2). The application must not change its processor binding
131 Upon successful completion these functions return 0. Otherwise, -1 is returned
149 HyperThreading and at least one physical processor has more than one hardware
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| H A D | cpc_shared_open.3cpc | 10 cpc_shared_rele, cpc_shared_close \- use CPU performance counters on processors
53 operate on the counters of a particular processor.
59 \fBthr_create\fR(3C)), that has in turn bound itself to a processor using
65 processors reflects the system-wide usage, instead of per-lwp usage.
76 accurately measure per-lwp and system-wide events, so there is an exclusive
83 on a per-lwp basis to other users.
92 failure, the functions return -1 and set \fBerrno\fR to indicate the reason.
101 counters system-wide.
111 are busy because they are already being used to measure system-wide events by
122 because the thread has been unbound from the processor it was bound to at open
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| H A D | cpc_event.3cpc | 8 cpc_event \- data structure to describe CPU performance counters
20 are common to all processors, and some that are processor-dependent. These
22 of the fields and the entire data structure are fixed per processor for any
62 The APIs are used to manipulate the highly processor-dependent control
65 portable code. The \fBce_pic\fR array elements contain 64-bit accumulated
66 counter values. The hardware registers are virtualized to 64-bit quantities
67 even though the underlying hardware only supports 32-bits (UltraSPARC) or
68 40-bits (Pentium) before overflow.
76 On SPARC V9 machines, the number of cycles spent running on the processor is
77 computed from samples of the processor-dependent \fB%tick\fR register, and
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| /illumos-gate/usr/src/data/perfmon/GLP/ |
| H A D | goldmontplus_core_v1.01.json | 249 …per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Include…
270 "BriefDescription": "Uops issued to the back end per cycle",
271 …ed includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, tho…
381 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
535 …e per cycle for each page walk occurring due to a demand data store. Includes cycles spent travers…
557 …per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not cou…
600 …"BriefDescription": "References per ICache line that are available in the ICache (hit). This event…
622 …"BriefDescription": "References per ICache line that are not available in the ICache (miss). This …
644 …"BriefDescription": "References per ICache line. This event counts differently than Intel processo…
755 … per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent travers…
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| /illumos-gate/usr/src/uts/sun4/sys/ |
| H A D | intreg.h | 42 #define MAX_INO (1 << INO_SIZE) /* Max Interrupt Number per group */
61 * Each interrupt source has a 2-bit state machine which ensures that
62 * software sees exactly one interrupt packet per assertion of the
67 #define ISM_PENDING 0x2 /* dispatched to a processor or is in transit */
70 * Per-Processor Soft Interrupt Register
81 * Per-Processor TICK Register and TICK_Compare registers
107 uchar_t filler[0x1000 - 0xc];
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| /illumos-gate/usr/src/uts/common/sys/ |
| H A D | isa_defs.h | 35 * be divided into two groups; characteristics of the processor and
36 * implementation choices for Solaris on a processor.
38 * Processor Characteristics:
41 * The natural byte order of the processor. A pointer to an int points
45 * The processor specific direction of stack growth. A push onto the
59 * The processor (or supported implementations of the processor)
60 * supports the ieee-754 floating point standard. No other floating
62 * floating point formats are expected to be cased on the ISA processor
70 * Hence, it has the properties of a processor characteristic.
77 * well. The values are expressed in "byte-alignment" units.
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| H A D | pg.h | 30 * Processor Groups
40 #include <sys/processor.h>
46 typedef int pgid_t; /* processor group id */
47 typedef uint_t pg_cid_t; /* processor group class id */
60 * Processor Group callbacks ops vector
61 * These provide a mechanism allowing per PG routines to invoked
72 * Processor group structure
113 * Per CPU processor group data
143 (GROUP_SIZE(&((pg_t *)pgrp)->pg_cpus) > 0 ? \
144 GROUP_ACCESS(&((pg_t *)pgrp)->pg_cpus, 0) : NULL)
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| H A D | sysdc_impl.h | 43 * Tracks per-processor-set information for SDC. Its main use is to
44 * implement per-processor-set breaks.
64 * Per-thread information, pointed to by t_cldata.
71 sysdc_pset_t *sdc_pset; /* the processor set bound to */
74 struct _kthread *sdc_thread; /* back-pointer, or NULL if freeable */
82 hrtime_t sdc_base_O; /* on-cpu time at last reset */
96 hrtime_t sdc_cur_O; /* on-cpu time at last prio check */
108 char sdl_pad[64 - sizeof (kmutex_t) - sizeof (sysdc_t *)];
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| /illumos-gate/usr/src/data/perfmon/GLM/ |
| H A D | goldmont_core_v13.json | 174 "BriefDescription": "Duration of D-side page-walks in cycles",
175 …"PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) pag…
195 "BriefDescription": "Duration of I-side pagewalks in cycles",
196 …"PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction…
216 "BriefDescription": "Duration of page-walks in cycles",
217 …"PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memo…
237 "BriefDescription": "Uops issued to the back end per cycle",
238 …ed includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, tho…
343 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
447 …"BriefDescription": "References per ICache line that are available in the ICache (hit). This event…
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| /illumos-gate/usr/src/uts/sun4u/opl/sys/ |
| H A D | opl_hwdesc.h | 39 #define HWD_SBS_PER_DOMAIN 32 /* System boards per domain */
40 #define HWD_CPUS_PER_CORE 4 /* Strands per physical core */
41 #define HWD_CORES_PER_CPU_CHIP 4 /* Cores per processor chip */
42 #define HWD_CPU_CHIPS_PER_CMU 4 /* Processor chips per CMU */
43 #define HWD_SCS_PER_CMU 4 /* System controllers per CMU */
44 #define HWD_DIMMS_PER_CMU 32 /* Memory DIMMs per CMU */
45 #define HWD_IOCS_PER_IOU 2 /* Oberon chips per I/O unit */
46 #define HWD_PCI_CHANNELS_PER_IOC 2 /* PCI channels per Oberon chip */
47 #define HWD_LEAVES_PER_PCI_CHANNEL 2 /* Leaves per PCI channel */
48 #define HWD_PCI_CHANNELS_PER_SB 4 /* PCI channels per system board */
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| /illumos-gate/usr/src/boot/efi/include/arm64/ |
| H A D | ProcessorBind.h | 2 Processor or Compiler specific defines and types for AArch64.
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
6 Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
16 /// Define the processor type so other code can make processor based choices
21 // Make sure we are using the correct packing rules per EFI specification
109 /// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
110 /// 8 bytes on supported 64-bit processor instructions)
115 /// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
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| /illumos-gate/usr/src/uts/common/disp/ |
| H A D | sysdc.c | 28 * --------------------------------------------
38 * without preemption from anything other than real-time and interrupt
44 * kernel to perform significant amounts of CPU-intensive work. One
50 * on a compression-heavy dataset can keep them busy for seconds on end.
51 * This causes human-time-scale dispatch latency bubbles for any other
62 * Duty Cycle = ----------------------
94 * if there are other priority-99 or higher threads on its CPU. These
124 * - Run queue balancing
130 * tries to keep the per-CPU run queues fairly balanced; if the CPU
149 * - LWPs and system processes
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| /illumos-gate/usr/src/uts/intel/io/coretemp/ |
| H A D | coretemp.c | 22 * temperature sensors exist on a per-core basis and optionally on a per-package
24 * processor's maximum junction temperature, often referred to as Tj. We
27 * down the datasheet. Unfortunately, the values here are often on a per-brand
31 * The temperature is exposed through /dev and uses a semi-standard sensor
32 * framework. We expose one minor node per CPU core and one minor node per CPU
33 * package, if that is supported. Reads are rate-limited in the driver at 100ms
34 * by default per the global variable coretemp_cache_ms.
132 * fixed for use outside of a panic-like context.
140 ASSERT(MUTEX_HELD(&ct->coretemp_mutex)); in coretemp_rdmsr()
142 if (CPU->cpu_id == cpu) { in coretemp_rdmsr()
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| /illumos-gate/usr/src/man/man3c/ |
| H A D | timer_create.3c | 16 .\" Standard for Information Technology -- Portable Operating System
18 .\" Copyright (C) 2001-2004 by the Institute of Electrical and Electronics
49 timer_create \- create a timer
69 The \fIevp\fR argument, if non-null, points to a \fBsigevent\fR structure. This
79 per-process timers. The following values for \fIclock_id\fR are supported:
95 non-adjustable, high-resolution clock
102 limited to, per-CPU timer sources. The actual hardware source used is
104 example, if the caller that created the timer were to change its processor
105 binding or its processor set, the system may elect to drive the timer with a
116 passed to the per-process timer calls. If an error occurs, the function returns
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| /illumos-gate/usr/src/boot/efi/include/i386/ |
| H A D | ProcessorBind.h | 2 Processor or Compiler specific defines and types for IA-32 architecture.
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
13 /// Define the processor type so other code can make processor based choices.
18 // Make sure we are using the correct packing rules per EFI specification
27 // This is legal ANSI C code so we disable the remark that is turned on with -Wall
118 /// 8-byte unsigned value.
122 /// 8-byte signed value.
126 /// 4-byte unsigned value.
130 /// 4-byte signed value.
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| /illumos-gate/usr/src/uts/sparc/sys/ |
| H A D | mcontext.h | 134 * struct fpu is the floating point processor state. struct fpu is the sum
139 * the floating point processor state. If a queue does exist, the field
143 * with the processor state, fpu_qcnt will be zeo and fpu_q will be NULL.
157 uint8_t fpu_q_entrysize; /* # of bytes per FQ entry */
171 uint8_t fpu_q_entrysize; /* # of bytes per FQ entry */
191 uint8_t fpu_q_entrysize; /* # of bytes per FQ entry */
225 * pointed to by xrs_ptr is platform-dependent.
254 typedef int64_t asrset_t[16]; /* %asr16 - > %asr31 */
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| /illumos-gate/usr/src/test/util-tests/tests/smbios/ |
| H A D | smbios_test_proc.c | 17 * SMBIOS processor tests. We build three main processors:
21 * 2. One based on SMBIOS 3.6 that has different values for the processor
23 * the processor family. Most of those were 3.x based. We use 3.6 so we can
24 * get the newer threads enabled field. A pre-3.x client should not see the
33 * Older revisions lengths per the SMBIOS spec.
48 * Construct a processor that we'll use throughout our tests. This fills in most
55 proc->smbpr_hdr.smbh_type = SMB_TYPE_PROCESSOR; in smbios_test_proc_fill()
56 proc->smbpr_hdr.smbh_len = sizeof (smb_processor_t); in smbios_test_proc_fill()
57 proc->smbpr_socket = 1; in smbios_test_proc_fill()
58 proc->smbpr_type = SMB_PRT_CENTRAL; in smbios_test_proc_fill()
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