Lines Matching +full:per +full:- +full:processor

9 cpc_set_restart \- bind request sets to hardware counters
13 cc [ \fIflag\fR\&.\|.\|. ] \fIfile\fR\&.\|.\|. \fB-lcpc\fR [ \fIlibrary\fR\&.\|.\|. ]
49 These functions program the processor's hardware counters according to the
66 virtualized 64-bit counters initialized to the preset values specified in
83 the \fIpctx\fR-\fIid\fR pair, where \fIpctx\fR refers to a handle returned from
94 any application has bound a set to a CPU, per-\fBLWP\fR counters are
97 \fBcpc_bind_cpu()\fR invalidates all currently bound per-\fBLWP\fR counter
100 \fBprocessor_bind\fR(2). The application must not change its processor binding
131 Upon successful completion these functions return 0. Otherwise, -1 is returned
149 HyperThreading and at least one physical processor has more than one hardware
192 For \fBcpc_bind_cpu()\fR, the specified processor does not exist.
206 For \fBcpc_bind_cpu()\fR, the specified processor is not online.
216 \fBCPC_OVF_NOTIFY_EMT\fR flag, but the underlying processor is not capable of
243 strings (a list of which can be obtained from the \fB-h\fR option of the
245 The \fBerror()\fR routine is assumed to be a user-provided routine analogous to
282         NULL)) == -1)
286         NULL)) == -1)
296 if (cpc_bind_curlwp(cpc, set, 0) == -1)
301         if (cpc_set_sample(cpc, set, before) == -1)
306         if (cpc_set_sample(cpc, set, after) == -1)
354      if (sig != SIGEMT || sip->si_code != EMT_CPCOVF) {
360      (void) printf("lwp%d - si_addr %p ucontext: %%pc %p %%sp %p\en",
361          _lwp_self(), (void *)sip->si_addr,
362          (void *)uap->uc_mcontext.gregs[PC],
363          (void *)uap->uc_mcontext.gregs[SP]);
395 #define PRESET (UINT64_MAX - 999ull)
402      if (sigaction(SIGEMT, &act, NULL) == -1)
412      if (cpc_bind_curlwp(cpc, set, 0) == -1)
438 MT-Level	Safe
457 all requests in the set, the bind function returns -1 and sets \fBerrno\fR to
463 to these limited hardware resources. See the processor manual as referenced by
464 \fBcpc_cpuref\fR(3CPC) for details about the underlying processor's
470 full 64-bit counter values are maintained without repeated sampling. Certain
471 hardware, such as the UltraSPARC processor, does not record which counter
478 The interrupt generated by the processor might not be particularly precise.
485 then as before, the control registers and counter are preset from the 64-bit
495 \fBcpc_caps\fR(3CPC), the processor is able to determine precisely which
499 If the capability is not present on the processor, the system sends a
507 to \fBUINT64_MAX\fR-\fBINT32_MAX\fR.
517 If the processor cannot detect counter overflow, bind will fail and return
528 hardware counters per physical processor. To use \fBcpc_bind_curlwp()\fR or
529 \fBcpc_bind_pctx()\fR to measure per-\fBLWP\fR events on a system with Pentium
531 system offline until each physical processor has only one hardware thread
532 online (See the \fB-p\fR option to \fBpsrinfo\fR(8)). If a second hardware
533 thread is brought online, all per-\fBLWP\fR bound contexts will be invalidated
537 Only one CPC set at a time can be bound to a physical processor with
539 set to a processor that shares a physical processor with a processor that
540 already has a CPU-bound set returns an error.
543 To measure the shared state on a Pentium 4 processor with HyperThreading, the
547 act on the sibling hardware thread sharing the physical processor with the CPU
555 CRU_ESCR3. See the processor documentation for details.