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/linux/drivers/pci/hotplug/
H A Dpciehp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
26 #include "../pcie/portdrv.h"
35 #define ctrl_dbg(ctrl, format, arg...) \ argument
36 pci_dbg(ctrl->pcie->port, format, ## arg)
37 #define ctrl_err(ctrl, format, arg...) \ argument
38 pci_err(ctrl->pcie->port, format, ## arg)
39 #define ctrl_info(ctrl, format, arg...) \ argument
40 pci_info(ctrl->pcie->port, format, ## arg)
[all …]
H A Dpciehp_hpc.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
37 * assert presence detect--and those will still work, they will
49 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) in ctrl_dev() argument
51 return ctrl->pcie->port; in ctrl_dev()
58 static inline int pciehp_request_irq(struct controller *ctrl) in pciehp_request_irq() argument
60 int retval, irq = ctrl->pcie->irq; in pciehp_request_irq()
63 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl, in pciehp_request_irq()
64 "pciehp_poll-%s", in pciehp_request_irq()
[all …]
H A Dpciehp_ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
33 static void set_slot_off(struct controller *ctrl) in set_slot_off() argument
39 if (POWER_CTRL(ctrl)) { in set_slot_off()
40 pciehp_power_off_slot(ctrl); in set_slot_off()
50 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, in set_slot_off()
55 * board_added - Called after a board has been added to the system.
56 * @ctrl: PCIe hotplug controller where board is added
61 static int board_added(struct controller *ctrl) in board_added() argument
[all …]
H A Dpciehp_core.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
16 * Greg Kroah-Hartman <greg@kroah.com>
43 MODULE_PARM_DESC(pciehp_poll_mode, "Using polling mechanism for hot-plug events or not");
51 static int init_slot(struct controller *ctrl) in init_slot() argument
60 return -ENOMEM; in init_slot()
62 ops->enable_slot = pciehp_sysfs_enable_slot; in init_slot()
63 ops->disable_slot = pciehp_sysfs_disable_slot; in init_slot()
64 ops->get_power_status = get_power_status; in init_slot()
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H A Dpciehp_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
25 * pciehp_configure_device() - enumerate PCI devices below a hotplug bridge
26 * @ctrl: PCIe hotplug controller
29 * Return 0 on success, %-EEXIST if the devices are already enumerated or
30 * %-ENODEV if enumeration failed.
32 int pciehp_configure_device(struct controller *ctrl) in pciehp_configure_device() argument
35 struct pci_dev *bridge = ctrl->pcie->port; in pciehp_configure_device()
36 struct pci_bus *parent = bridge->subordinate; in pciehp_configure_device()
[all …]
/linux/drivers/pci/controller/
H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
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H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe endpoint controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
28 * @rockchip: Rockchip PCIe controller
37 * IRQ) TLP through the PCIe bus.
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H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
258 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
259 * entries, one entry per PCIe port. These field definitions and desired
364 struct tegra_pcie *pcie; member
377 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
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/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
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H A Dmarvell,armada8k-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 7K/8K PCIe interface
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
13 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
20 - marvell,armada8k-pcie
22 - compatible
25 - $ref: snps,dw-pcie.yaml#
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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epc.h>
15 #include "pcie-cadence.h"
22 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
30 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_get_fn_from_vfn()
31 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
32 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
33 fn = fn + first_vf_offset + ((vfn - 1) * stride); in cdns_pcie_get_fn_from_vfn()
[all …]
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-layerscape-gen4.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
5 * Copyright 2019-2020 NXP
23 #include "pcie-mobiveil.h"
37 #define to_ls_g4_pcie(x) platform_get_drvdata((x)->pdev)
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,j721s2-c71-dsp";
13 reg-names = "l2sram", "l1dram";
15 firmware-name = "j784s4-c71_3-fw";
17 ti,sci-dev-id = <40>;
18 ti,sci-proc-ids = <0x33 0xff>;
22 pcie2_rc: pcie@2920000 {
23 compatible = "ti,j784s4-pcie-host";
30 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
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H A Dk3-j784s4-evm-pcie0-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
32 #address-cells = <2>;
33 #size-cells = <2>;
34 interrupt-parent = <&gic500>;
36 pcie0_ep: pcie-ep@2900000 {
[all …]
/linux/drivers/pci/
H A Drebar.c1 // SPDX-License-Identifier: GPL-2.0
22 * pci_rebar_bytes_to_size - Convert size in bytes to PCI BAR Size
26 * (PCIe r6.2, sec. 7.8.6.3).
28 * Return: encoded BAR Size as defined in the PCIe spec (0=1MB, 31=128TB)
36 return max(ilog2(bytes), rebar_minsize) - rebar_minsize; in pci_rebar_bytes_to_size()
41 * pci_rebar_size_to_bytes - Convert encoded BAR Size to size in bytes
42 * @size: encoded BAR Size as defined in the PCIe spec (0=1MB, 31=128TB)
54 pdev->rebar_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); in pci_rebar_init()
58 * pci_rebar_find_pos - find position of resize control reg for BAR
65 * * %-ENOTSUPP if resizable BARs are not supported at all,
[all …]
H A Dnpem.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe Enclosure management driver created for LED interfaces based on
5 * they blink - it is hardware defined.
7 * The driver name refers to Native PCIe Enclosure Management. It is
10 * Native PCIe Enclosure Management (NPEM)
11 * PCIe Base Specification r6.1 sec 6.28, 7.9.19
13 * _DSM Definitions for PCIe SSD Status LED
20 * Copyright (c) 2021-2022 Dell Inc.
21 * Copyright (c) 2023-2024 Intel Corporation
65 /* _DSM PCIe SSD LED States correspond to NPEM register values */
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,j721e-system-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@kernel.org>
23 - Roger Quadros <rogerq@kernel.org>
28 - enum:
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-histb.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for HiSilicon STB SoCs
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
24 #include "pcie-designware.h"
26 #define to_histb_pcie(x) dev_get_drvdata((x)->dev)
62 void __iomem *ctrl; member
69 return readl(histb_pcie->ctrl + reg); in histb_pcie_readl()
74 writel(val, histb_pcie->ctrl + reg); in histb_pcie_writel()
110 histb_pcie_dbi_r_mode(&pci->pp, true); in histb_pcie_read_dbi()
112 histb_pcie_dbi_r_mode(&pci->pp, false); in histb_pcie_read_dbi()
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/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
[all …]
/linux/drivers/net/wwan/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
40 tristate "MHI WWAN control driver for QCOM-based PCIe modems"
43 MHI WWAN CTRL allows QCOM-based PCIe modems to expose different modem
53 tristate "MHI WWAN MBIM network driver for QCOM-based PCIe modems"
56 MHI WWAN MBIM is a WWAN network driver for QCOM-based PCIe modems.
65 tristate "Qualcomm BAM-DMUX WWAN network driver"
81 RPMSG WWAN CTRL allows modems available via RPMSG channels to expose
109 tristate "MediaTek PCIe 5G WWAN modem T7xx device"
113 Enables MediaTek PCIe based 5G WWAN modem (T7xx series) device.
/linux/drivers/nvme/target/
H A Dpassthru.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Western Digital Corporation or its
7 * Copyright (c) 2019-2020, Eideticom Inc.
23 void nvmet_passthrough_override_cap(struct nvmet_ctrl *ctrl) in nvmet_passthrough_override_cap() argument
29 if (!nvme_multi_css(ctrl->subsys->passthru_ctrl)) in nvmet_passthrough_override_cap()
30 ctrl->cap &= ~(1ULL << 43); in nvmet_passthrough_override_cap()
35 struct nvmet_ctrl *ctrl = req->sq->ctrl; in nvmet_passthru_override_id_descs() local
42 if (!ctrl->subsys->clear_ids) in nvmet_passthru_override_id_descs()
56 if (cur->nidl == 0) in nvmet_passthru_override_id_descs()
58 if (cur->nidt == NVME_NIDT_CSI) { in nvmet_passthru_override_id_descs()
[all …]
/linux/drivers/comedi/drivers/
H A Dcb_pcimdas.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Comedi driver for Computer Boards PCIM-DAS1602/16 and PCIe-DAS1602/16
6 * COMEDI - Linux Control and Measurement Device Interface
13 * Devices: [ComputerBoards] PCIM-DAS1602/16 (cb_pcimdas), PCIe-DAS1602/16
18 * Written to support the PCIM-DAS1602/16 and PCIe-DAS1602/16.
31 * https://www.mccdaq.com/PDFs/Manuals/pcim-das1602-16.pdf
32 * https://www.mccdaq.com/PDFs/Manuals/pcie-das1602-16.pdf
49 * PCI Bar 2 Register map (devpriv->daqio)
56 * PCI Bar 3 Register map (devpriv->BADR3)
107 * PCI Bar 4 Register map (dev->iobase)
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/phy/pcie.h>
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
25 /* Parameters for the waiting for PCIe PHY PLL to lock */
93 struct regmap *ctrl; member
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
121 struct device *dev = priv->dev; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
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/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
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